Sam Parker 12b4374cd5 [AArch64] Port atomic rmw to ISLE (#4021) ...

Also fix and extend the current implementation:
- AtomicRMWOp::Clr != AtomicRmwOp::And, as the input needs to be
  inverted first.
- Inputs to the cmp for the RMWLoop case are sign-extended when
  needed.
- Lower Xchg to Swp.
- Lower Sub to Add with a negated input.
- Added more runtests.

Copyright (c) 2022, Arm Limited.

2022-04-27 13:13:59 -07:00

..

filetests

[AArch64] Port atomic rmw to ISLE (#4021)

2022-04-27 13:13:59 -07:00

src

Cranelift: ensure ISA level needed for SIMD is present when SIMD is enabled. (#3816)

2022-02-16 17:29:30 -08:00

Cargo.toml

Bump Wasmtime to 0.37.0 (#3994)

2022-04-05 09:24:28 -05:00

LICENSE

moved crates in lib/ to src/, renamed crates, modified some files' text (#660)

2019-01-28 15:56:54 -08:00