69f70fc61d
This is implemented as a macro with a conditional jump over a ud2. This way, we don't have to split up EBBs at every conditional trap.
301 lines
10 KiB
Rust
301 lines
10 KiB
Rust
//! Emitting binary Intel machine code.
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use binemit::{CodeSink, Reloc, bad_encoding};
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use ir::{Function, Inst, Ebb, InstructionData, Opcode};
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use ir::condcodes::{CondCode, IntCC, FloatCC};
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use isa::{RegUnit, StackRef, StackBase, StackBaseMask};
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use regalloc::RegDiversions;
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use super::registers::RU;
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include!(concat!(env!("OUT_DIR"), "/binemit-intel.rs"));
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// Convert a stack base to the corresponding register.
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fn stk_base(base: StackBase) -> RegUnit {
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let ru = match base {
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StackBase::SP => RU::rsp,
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StackBase::FP => RU::rbp,
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StackBase::Zone => unimplemented!(),
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};
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ru as RegUnit
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}
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// Mandatory prefix bytes for Mp* opcodes.
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const PREFIX: [u8; 3] = [0x66, 0xf3, 0xf2];
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// Second byte for three-byte opcodes for mm=0b10 and mm=0b11.
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const OP3_BYTE2: [u8; 2] = [0x38, 0x3a];
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// A REX prefix with no bits set: 0b0100WRXB.
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const BASE_REX: u8 = 0b0100_0000;
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// Create a single-register REX prefix, setting the B bit to bit 3 of the register.
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// This is used for instructions that encode a register in the low 3 bits of the opcode and for
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// instructions that use the ModR/M `reg` field for something else.
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fn rex1(reg_b: RegUnit) -> u8 {
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let b = ((reg_b >> 3) & 1) as u8;
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BASE_REX | b
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}
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// Create a dual-register REX prefix, setting:
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//
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// REX.B = bit 3 of r/m register, or SIB base register when a SIB byte is present.
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// REX.R = bit 3 of reg register.
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fn rex2(rm: RegUnit, reg: RegUnit) -> u8 {
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let b = ((rm >> 3) & 1) as u8;
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let r = ((reg >> 3) & 1) as u8;
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BASE_REX | b | (r << 2)
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}
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// Emit a REX prefix.
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//
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// The R, X, and B bits are computed from registers using the functions above. The W bit is
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// extracted from `bits`.
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fn rex_prefix<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(rex & 0xf8, BASE_REX);
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let w = ((bits >> 15) & 1) as u8;
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sink.put1(rex | (w << 3));
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}
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// Emit a single-byte opcode with no REX prefix.
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fn put_op1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8f00, 0, "Invalid encoding bits for Op1*");
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Op1 encoding");
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sink.put1(bits as u8);
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}
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// Emit a single-byte opcode with REX prefix.
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fn put_rexop1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0f00, 0, "Invalid encoding bits for Op1*");
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rex_prefix(bits, rex, sink);
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode: 0F XX
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fn put_op2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8f00, 0x0400, "Invalid encoding bits for Op2*");
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Op2 encoding");
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode: 0F XX with REX prefix.
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fn put_rexop2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0f00, 0x0400, "Invalid encoding bits for RexOp2*");
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rex_prefix(bits, rex, sink);
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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// Emit single-byte opcode with mandatory prefix.
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fn put_mp1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8c00, 0, "Invalid encoding bits for Mp1*");
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let pp = (bits >> 8) & 3;
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sink.put1(PREFIX[(pp - 1) as usize]);
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Mp1 encoding");
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sink.put1(bits as u8);
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}
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// Emit single-byte opcode with mandatory prefix and REX.
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fn put_rexmp1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0c00, 0, "Invalid encoding bits for Mp1*");
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let pp = (bits >> 8) & 3;
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sink.put1(PREFIX[(pp - 1) as usize]);
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rex_prefix(bits, rex, sink);
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode (0F XX) with mandatory prefix.
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fn put_mp2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8c00, 0x0400, "Invalid encoding bits for Mp2*");
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let pp = (bits >> 8) & 3;
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sink.put1(PREFIX[(pp - 1) as usize]);
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Mp2 encoding");
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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// Emit two-byte opcode (0F XX) with mandatory prefix and REX.
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fn put_rexmp2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0c00, 0x0400, "Invalid encoding bits for Mp2*");
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let pp = (bits >> 8) & 3;
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sink.put1(PREFIX[(pp - 1) as usize]);
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rex_prefix(bits, rex, sink);
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sink.put1(0x0f);
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sink.put1(bits as u8);
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}
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// Emit three-byte opcode (0F 3[8A] XX) with mandatory prefix.
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fn put_mp3<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x8800, 0x0800, "Invalid encoding bits for Mp3*");
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let pp = (bits >> 8) & 3;
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sink.put1(PREFIX[(pp - 1) as usize]);
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debug_assert_eq!(rex, BASE_REX, "Invalid registers for REX-less Mp3 encoding");
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let mm = (bits >> 10) & 3;
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sink.put1(0x0f);
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sink.put1(OP3_BYTE2[(mm - 2) as usize]);
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sink.put1(bits as u8);
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}
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// Emit three-byte opcode (0F 3[8A] XX) with mandatory prefix and REX
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fn put_rexmp3<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
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debug_assert_eq!(bits & 0x0800, 0x0800, "Invalid encoding bits for Mp3*");
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let pp = (bits >> 8) & 3;
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sink.put1(PREFIX[(pp - 1) as usize]);
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rex_prefix(bits, rex, sink);
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let mm = (bits >> 10) & 3;
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sink.put1(0x0f);
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sink.put1(OP3_BYTE2[(mm - 2) as usize]);
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sink.put1(bits as u8);
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}
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/// Emit a ModR/M byte for reg-reg operands.
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fn modrm_rr<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
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let reg = reg as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b11000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a ModR/M byte where the reg bits are part of the opcode.
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fn modrm_r_bits<CS: CodeSink + ?Sized>(rm: RegUnit, bits: u16, sink: &mut CS) {
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let reg = (bits >> 12) as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b11000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a mode 00 ModR/M byte. This is a register-indirect addressing mode with no offset.
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/// Registers %rsp and %rbp are invalid for `rm`, %rsp indicates a SIB byte, and %rbp indicates an
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/// absolute immediate 32-bit address.
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fn modrm_rm<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
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let reg = reg as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b00000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a mode 00 Mod/RM byte, with a rip-relative displacement in 64-bit mode. Effective address
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/// is calculated by adding displacement to 64-bit rip of next instruction. See intel Sw dev manual
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/// section 2.2.1.6.
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fn modrm_riprel<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
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modrm_rm(0b101, reg, sink)
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}
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/// Emit a mode 01 ModR/M byte. This is a register-indirect addressing mode with 8-bit
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/// displacement.
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/// Register %rsp is invalid for `rm`. It indicates the presence of a SIB byte.
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fn modrm_disp8<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
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let reg = reg as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b01000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a mode 10 ModR/M byte. This is a register-indirect addressing mode with 32-bit
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/// displacement.
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/// Register %rsp is invalid for `rm`. It indicates the presence of a SIB byte.
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fn modrm_disp32<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
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let reg = reg as u8 & 7;
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let rm = rm as u8 & 7;
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let mut b = 0b10000000;
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b |= reg << 3;
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b |= rm;
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sink.put1(b);
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}
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/// Emit a mode 10 ModR/M byte indicating that a SIB byte is present.
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fn modrm_sib_disp32<CS: CodeSink + ?Sized>(reg: RegUnit, sink: &mut CS) {
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modrm_disp32(0b100, reg, sink);
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}
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/// Emit a SIB byte with a base register and no scale+index.
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fn sib_noindex<CS: CodeSink + ?Sized>(base: RegUnit, sink: &mut CS) {
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let base = base as u8 & 7;
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// SIB SS_III_BBB.
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let mut b = 0b00_100_000;
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b |= base;
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sink.put1(b);
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}
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/// Get the low 4 bits of an opcode for an integer condition code.
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///
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/// Add this offset to a base opcode for:
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///
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/// ---- 0x70: Short conditional branch.
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/// 0x0f 0x80: Long conditional branch.
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/// 0x0f 0x90: SetCC.
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///
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fn icc2opc(cond: IntCC) -> u16 {
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use ir::condcodes::IntCC::*;
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match cond {
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// 0x0 = Overflow.
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// 0x1 = !Overflow.
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UnsignedLessThan => 0x2,
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UnsignedGreaterThanOrEqual => 0x3,
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Equal => 0x4,
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NotEqual => 0x5,
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UnsignedLessThanOrEqual => 0x6,
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UnsignedGreaterThan => 0x7,
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// 0x8 = Sign.
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// 0x9 = !Sign.
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// 0xa = Parity even.
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// 0xb = Parity odd.
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SignedLessThan => 0xc,
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SignedGreaterThanOrEqual => 0xd,
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SignedLessThanOrEqual => 0xe,
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SignedGreaterThan => 0xf,
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}
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}
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/// Get the low 4 bits of an opcode for a floating point condition code.
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///
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/// The ucomiss/ucomisd instructions set the EFLAGS bits CF/PF/CF like this:
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///
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/// ZPC OSA
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/// UN 111 000
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/// GT 000 000
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/// LT 001 000
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/// EQ 100 000
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///
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/// Not all floating point condition codes are supported.
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fn fcc2opc(cond: FloatCC) -> u16 {
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use ir::condcodes::FloatCC::*;
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match cond {
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Ordered => 0xb, // EQ|LT|GT => *np (P=0)
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Unordered => 0xa, // UN => *p (P=1)
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OrderedNotEqual => 0x5, // LT|GT => *ne (Z=0),
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UnorderedOrEqual => 0x4, // UN|EQ => *e (Z=1)
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GreaterThan => 0x7, // GT => *a (C=0&Z=0)
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GreaterThanOrEqual => 0x3, // GT|EQ => *ae (C=0)
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UnorderedOrLessThan => 0x2, // UN|LT => *b (C=1)
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UnorderedOrLessThanOrEqual => 0x6, // UN|LT|EQ => *be (Z=1|C=1)
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Equal | // EQ
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NotEqual | // UN|LT|GT
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LessThan | // LT
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LessThanOrEqual | // LT|EQ
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UnorderedOrGreaterThan | // UN|GT
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UnorderedOrGreaterThanOrEqual // UN|GT|EQ
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=> panic!("{} not supported", cond),
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}
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}
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/// Emit a single-byte branch displacement to `destination`.
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fn disp1<CS: CodeSink + ?Sized>(destination: Ebb, func: &Function, sink: &mut CS) {
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let delta = func.offsets[destination].wrapping_sub(sink.offset() + 1);
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sink.put1(delta as u8);
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}
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/// Emit a single-byte branch displacement to `destination`.
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fn disp4<CS: CodeSink + ?Sized>(destination: Ebb, func: &Function, sink: &mut CS) {
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let delta = func.offsets[destination].wrapping_sub(sink.offset() + 4);
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sink.put4(delta);
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}
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