9bd9c628aa
We had previously fixed a bug in which constant shift amounts should be masked to modulo the number of bits in the operand; however, we did not fix the analogous case for shifts incorporated into the second register argument of ALU instructions that support integrated shifts. This failure to mask resulted in illegal instructions being generated, e.g. in https://bugzilla.mozilla.org/show_bug.cgi?id=1653502. This PR fixes the issue by masking the amount, as the shift semantics require.
383 lines
7.4 KiB
Plaintext
383 lines
7.4 KiB
Plaintext
test compile
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target aarch64
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function %f1(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = iadd.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: add x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f2(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = isub.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f3(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = imul.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: madd x0, x0, x1, xzr
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f4(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = umulhi.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: umulh x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f5(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = smulhi.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: smulh x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f6(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sdiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: adds xzr, x1, #1
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; nextln: ccmp x0, #1, #nzcv, eq
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; nextln: b.vc 8 ; udf
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; nextln: mov x0, x2
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f7(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x2, #2
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; nextln: sdiv x1, x0, x2
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; nextln: cbnz x2, 8 ; udf
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; nextln: adds xzr, x2, #1
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; nextln: ccmp x0, #1, #nzcv, eq
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; nextln: b.vc 8 ; udf
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; nextln: mov x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f8(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = udiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f9(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = udiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x1, #2
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f10(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = srem.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sdiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f11(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = urem.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: udiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f12(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x3, w0
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; nextln: sxtw x2, w1
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; nextln: sdiv x0, x3, x2
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; nextln: cbnz x2, 8 ; udf
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; nextln: adds wzr, w2, #1
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; nextln: ccmp w3, #1, #nzcv, eq
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; nextln: b.vc 8 ; udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f13(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x0, w0
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; nextln: movz x1, #2
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; nextln: sxtw x2, w1
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; nextln: sdiv x1, x0, x2
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; nextln: cbnz x2, 8 ; udf
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; nextln: adds wzr, w2, #1
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; nextln: ccmp w0, #1, #nzcv, eq
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; nextln: b.vc 8 ; udf
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; nextln: mov x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f14(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = udiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: mov w1, w1
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f15(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = udiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: movz x1, #2
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f16(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = srem.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x0, w0
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; nextln: sxtw x1, w1
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; nextln: sdiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f17(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = urem.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: mov w1, w1
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; nextln: udiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f18(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = band.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: and x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f19(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bor.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orr x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f20(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bxor.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: eor x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f21(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = band_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: bic x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f22(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bor_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orn x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f23(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bxor_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: eon x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f24(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bnot.i64 v0
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orn x0, xzr, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f25(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = iconst.i32 53
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v3 = ishl.i32 v0, v2
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v4 = isub.i32 v1, v3
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return v4
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub w0, w1, w0, LSL 21
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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