Jakob Stoklund Olesen e9907fbdd6 Add RISC-V encodings for supported icmp variants. ...

Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.

2017-03-31 13:47:07 -07:00

..

arm32

Add a section about implementation limits.

2017-02-24 11:08:15 -08:00

arm64

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

intel

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

riscv

Add RISC-V encodings for supported icmp variants.

2017-03-31 13:47:07 -07:00

__init__.py

Fixed for mypy 0.501.

2017-03-03 09:08:28 -08:00