e95ffe4413
* Fix StructReturn handling: properly mark the clobber, and offset actual rets. The legalization of `StructReturn` was causing issues in the new call-handling code: the `StructReturn` ret was included in the `SigData` as if it were an actual CLIF-level return value, but it is not. Prior to using regalloc constraints for return values, we unconditionally included rax (or the architecture's usual return register) as a def, so it would be properly handled as "clobbered" by the regalloc. With the new scheme, we include defs on the call only for CLIF-level outputs. Callees with `StructReturn` args were thus not known to clobber the return-value register, and values might be corrupted. This PR updates the code to include a `StructReturn` ret as a clobber rather than a returned value in the relevant spots. I observed it causing saves/restores of rax in some CLIF that @bjorn3 provided me, but I was having difficulty minimizing this into a test-case that I would be comfortable including as a precise-output case (including the whole thing verbatim would lock down a bunch of other irrelevant details and cause test-update noise later). If we can find a more minimized example I'm happy to include it as a filetest. Fixes #5018.
501 lines
8.8 KiB
Plaintext
501 lines
8.8 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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set enable_probestack=false
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target aarch64
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function %f1(i64) -> i64 {
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fn0 = %g(i64) -> i64
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block0(v0: i64):
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v1 = call fn0(v0)
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return v1
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
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; blr x4
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; ldp fp, lr, [sp], #16
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; ret
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function %f2(i32) -> i64 {
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fn0 = %g(i32 uext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
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; blr x4
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; ldp fp, lr, [sp], #16
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; ret
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function %f3(i32) -> i32 uext {
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block0(v0: i32):
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return v0
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}
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; block0:
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; ret
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function %f4(i32) -> i64 {
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fn0 = %g(i32 sext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
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; blr x4
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; ldp fp, lr, [sp], #16
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; ret
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function %f5(i32) -> i32 sext {
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block0(v0: i32):
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return v0
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}
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; block0:
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; ret
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function %f6(i8) -> i64 {
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fn0 = %g(i32, i32, i32, i32, i32, i32, i32, i32, i8 sext) -> i64
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block0(v0: i8):
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v1 = iconst.i32 42
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v2 = call fn0(v1, v1, v1, v1, v1, v1, v1, v1, v0)
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return v2
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; mov x8, x0
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; sub sp, sp, #16
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; virtual_sp_offset_adjust 16
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; movz x0, #42
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; movz x1, #42
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; movz x2, #42
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; movz x3, #42
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; movz x4, #42
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; movz x5, #42
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; movz x6, #42
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; movz x7, #42
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; strb w8, [sp]
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; ldr x8, 8 ; b 12 ; data TestCase(%g) + 0
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; blr x8
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; add sp, sp, #16
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; virtual_sp_offset_adjust -16
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; ldp fp, lr, [sp], #16
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; ret
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function %f7(i8) -> i32, i32, i32, i32, i32, i32, i32, i32, i8 sext {
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block0(v0: i8):
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v1 = iconst.i32 42
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return v1, v1, v1, v1, v1, v1, v1, v1, v0
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}
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; block0:
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; mov x8, x0
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; mov x13, x1
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; movz x0, #42
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; movz x1, #42
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; movz x2, #42
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; movz x3, #42
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; movz x4, #42
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; movz x5, #42
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; movz x6, #42
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; movz x7, #42
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; mov x11, x8
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; strb w11, [x13]
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; ret
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function %f8() {
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fn0 = %g0() -> f32
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fn1 = %g1() -> f64
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fn2 = %g2()
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fn3 = %g3(f32)
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fn4 = %g4(f64)
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block0:
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v0 = call fn0()
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v1 = call fn1()
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v2 = call fn1()
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call fn2()
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call fn3(v0)
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call fn4(v1)
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call fn4(v2)
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; sub sp, sp, #48
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; block0:
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; ldr x9, 8 ; b 12 ; data TestCase(%g0) + 0
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; blr x9
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; str q0, [sp, #32]
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; ldr x9, 8 ; b 12 ; data TestCase(%g1) + 0
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; blr x9
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; str q0, [sp, #16]
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; ldr x9, 8 ; b 12 ; data TestCase(%g1) + 0
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; blr x9
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; str q0, [sp]
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; ldr x9, 8 ; b 12 ; data TestCase(%g2) + 0
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; blr x9
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; ldr x10, 8 ; b 12 ; data TestCase(%g3) + 0
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; ldr q0, [sp, #32]
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; blr x10
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; ldr x11, 8 ; b 12 ; data TestCase(%g4) + 0
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; ldr q0, [sp, #16]
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; blr x11
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; ldr x12, 8 ; b 12 ; data TestCase(%g4) + 0
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; ldr q0, [sp]
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; blr x12
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; add sp, sp, #48
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; ldp fp, lr, [sp], #16
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; ret
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function %f9() {
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fn0 = %g0() -> i8x16
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fn1 = %g1()
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fn2 = %g2(i8x16)
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block0:
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v0 = call fn0()
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v1 = call fn0()
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v2 = call fn0()
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call fn1()
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call fn2(v0)
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call fn2(v1)
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call fn2(v2)
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; sub sp, sp, #48
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; block0:
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; ldr x9, 8 ; b 12 ; data TestCase(%g0) + 0
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; blr x9
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; str q0, [sp, #32]
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; ldr x9, 8 ; b 12 ; data TestCase(%g0) + 0
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; blr x9
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; str q0, [sp, #16]
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; ldr x9, 8 ; b 12 ; data TestCase(%g0) + 0
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; blr x9
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; str q0, [sp]
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; ldr x9, 8 ; b 12 ; data TestCase(%g1) + 0
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; blr x9
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; ldr x10, 8 ; b 12 ; data TestCase(%g2) + 0
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; ldr q0, [sp, #32]
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; blr x10
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; ldr x11, 8 ; b 12 ; data TestCase(%g2) + 0
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; ldr q0, [sp, #16]
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; blr x11
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; ldr x12, 8 ; b 12 ; data TestCase(%g2) + 0
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; ldr q0, [sp]
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; blr x12
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; add sp, sp, #48
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; ldp fp, lr, [sp], #16
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; ret
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function %f10() {
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fn0 = %g0() -> f32
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fn1 = %g1() -> f64
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fn2 = %g2() -> i8x16
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fn3 = %g3()
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fn4 = %g4(f32)
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fn5 = %g5(f64)
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fn6 = %g6(i8x16)
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block0:
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v0 = call fn0()
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v1 = call fn1()
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v2 = call fn2()
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call fn3()
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call fn4(v0)
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call fn5(v1)
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call fn6(v2)
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; sub sp, sp, #48
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; block0:
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; ldr x9, 8 ; b 12 ; data TestCase(%g0) + 0
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; blr x9
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; str q0, [sp, #32]
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; ldr x9, 8 ; b 12 ; data TestCase(%g1) + 0
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; blr x9
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; str q0, [sp, #16]
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; ldr x9, 8 ; b 12 ; data TestCase(%g2) + 0
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; blr x9
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; str q0, [sp]
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; ldr x9, 8 ; b 12 ; data TestCase(%g3) + 0
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; blr x9
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; ldr x10, 8 ; b 12 ; data TestCase(%g4) + 0
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; ldr q0, [sp, #32]
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; blr x10
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; ldr x11, 8 ; b 12 ; data TestCase(%g5) + 0
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; ldr q0, [sp, #16]
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; blr x11
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; ldr x12, 8 ; b 12 ; data TestCase(%g6) + 0
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; ldr q0, [sp]
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; blr x12
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; add sp, sp, #48
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; ldp fp, lr, [sp], #16
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; ret
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function %f11(i128, i64) -> i64 {
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block0(v0: i128, v1: i64):
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v2, v3 = isplit v0
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return v3
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}
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; block0:
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; mov x0, x1
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; ret
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function %f11_call(i64) -> i64 {
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fn0 = %f11(i128, i64) -> i64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v1, v0
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v3 = call fn0(v2, v1)
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return v3
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; mov x1, x0
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; movz x0, #42
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; movz x2, #42
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; ldr x7, 8 ; b 12 ; data TestCase(%f11) + 0
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; blr x7
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; ldp fp, lr, [sp], #16
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; ret
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function %f12(i64, i128) -> i64 {
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block0(v0: i64, v1: i128):
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v2, v3 = isplit v1
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return v2
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}
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; block0:
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; mov x0, x2
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; ret
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function %f12_call(i64) -> i64 {
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fn0 = %f12(i64, i128) -> i64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v0, v1
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v3 = call fn0(v1, v2)
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return v3
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; mov x2, x0
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; movz x3, #42
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; movz x0, #42
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; ldr x7, 8 ; b 12 ; data TestCase(%f12) + 0
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; blr x7
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; ldp fp, lr, [sp], #16
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; ret
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function %f13(i64, i128) -> i64 apple_aarch64 {
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block0(v0: i64, v1: i128):
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v2, v3 = isplit v1
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return v2
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}
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; block0:
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; mov x0, x1
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; ret
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function %f13_call(i64) -> i64 apple_aarch64 {
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fn0 = %f13(i64, i128) -> i64 apple_aarch64
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block0(v0: i64):
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v1 = iconst.i64 42
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v2 = iconcat v0, v1
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v3 = call fn0(v1, v2)
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return v3
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; mov x1, x0
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; movz x2, #42
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; movz x0, #42
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; ldr x7, 8 ; b 12 ; data TestCase(%f13) + 0
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; blr x7
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; ldp fp, lr, [sp], #16
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; ret
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function %f14(i128, i128, i128, i64, i128) -> i128 {
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block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
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return v4
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; ldr x0, [fp, #16]
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; ldr x1, [fp, #24]
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; ldp fp, lr, [sp], #16
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; ret
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function %f14_call(i128, i64) -> i128 {
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fn0 = %f14(i128, i128, i128, i64, i128) -> i128
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block0(v0: i128, v1: i64):
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v2 = call fn0(v0, v0, v0, v1, v0)
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return v2
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; mov x6, x2
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; sub sp, sp, #16
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; virtual_sp_offset_adjust 16
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; str x0, [sp]
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; mov x4, x0
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; str x1, [sp, #8]
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; mov x5, x1
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; ldr x12, 8 ; b 12 ; data TestCase(%f14) + 0
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; mov x0, x4
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; mov x2, x4
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; mov x1, x5
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; mov x3, x5
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; blr x12
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; add sp, sp, #16
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; virtual_sp_offset_adjust -16
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; ldp fp, lr, [sp], #16
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; ret
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function %f15(i128, i128, i128, i64, i128) -> i128 apple_aarch64{
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block0(v0: i128, v1: i128, v2: i128, v3: i64, v4: i128):
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return v4
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; ldr x0, [fp, #16]
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; ldr x1, [fp, #24]
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; ldp fp, lr, [sp], #16
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; ret
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function %f15_call(i128, i64) -> i128 apple_aarch64 {
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fn0 = %f15(i128, i128, i128, i64, i128) -> i128 apple_aarch64
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block0(v0: i128, v1: i64):
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v2 = call fn0(v0, v0, v0, v1, v0)
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return v2
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; mov x6, x2
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; sub sp, sp, #16
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; virtual_sp_offset_adjust 16
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; str x0, [sp]
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; mov x4, x0
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; str x1, [sp, #8]
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; mov x5, x1
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; ldr x12, 8 ; b 12 ; data TestCase(%f15) + 0
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; mov x0, x4
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; mov x2, x4
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; mov x1, x5
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; mov x3, x5
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; blr x12
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; add sp, sp, #16
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; virtual_sp_offset_adjust -16
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; ldp fp, lr, [sp], #16
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; ret
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function %f16() -> i32, i32 wasmtime_system_v {
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block0:
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v0 = iconst.i32 0
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v1 = iconst.i32 1
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return v0, v1
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}
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; block0:
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; mov x11, x0
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; movz x0, #0
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; movz x7, #1
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; str w7, [x11]
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; ret
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function %f17(i64 sret) {
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block0(v0: i64):
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v1 = iconst.i64 42
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store v1, v0
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return
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}
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; block0:
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; mov x5, x8
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; movz x4, #42
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; str x4, [x8]
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; ret
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function %f18(i64) -> i64 {
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fn0 = %g(i64 sret) -> i64
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block0(v0: i64):
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v1 = call fn0(v0)
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return v1
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; block0:
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; mov x8, x0
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; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
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; blr x4
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; ldp fp, lr, [sp], #16
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; ret
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function %f18(i64 sret) {
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fn0 = %g(i64 sret)
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block0(v0: i64):
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call fn0(v0)
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; str x24, [sp, #-16]!
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; block0:
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; mov x24, x8
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; ldr x4, 8 ; b 12 ; data TestCase(%g) + 0
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; blr x4
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; mov x8, x24
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; ldr x24, [sp], #16
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; ldp fp, lr, [sp], #16
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; ret
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