e8881b2cc0
This PR makes use of the new implicit-conversion feature of the ISLE DSL that was introduced in #3807 in order to make the lowering rules significantly simpler and more concise. The basic idea is to eliminate the repetitive and mechanical use of terms that convert from one type to another when there is only one real way to do the conversion -- for example, to go from a `WritableReg` to a `Reg`, the only sensible way is to use `writable_reg_to_reg`. This PR generally takes any term of the form "A_to_B" and makes it an automatic conversion, as well as some others that are similar in spirit. The notable exception to the pure-value-convsion category is the `put_in_reg` family of operations, which actually do have side-effects. However, as noted in the doc additions in #3807, this is fine as long as the side-effects are idempotent. And on balance, making `put_in_reg` automatic is a significant clarity win -- together with other operand converters, it enables rules like: ``` ;; Add two registers. (rule (lower (has_type (fits_in_64 ty) (iadd x y))) (add ty x y)) ``` There may be other converters that we could define to make the rules even simpler; we can make such improvements as we think of them, but this should be a good start!
1127 lines
42 KiB
Common Lisp
1127 lines
42 KiB
Common Lisp
;; aarch64 instruction selection and CLIF-to-MachInst lowering.
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;; The main lowering constructor term: takes a clif `Inst` and returns the
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;; register(s) within which the lowered instruction's result values live.
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(decl lower (Inst) ValueRegs)
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;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (iconst (u64_from_imm64 n))))
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(imm ty n))
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;;;; Rules for `bconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (bconst $false)))
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(imm ty 0))
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(rule (lower (has_type ty (bconst $true)))
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(imm ty 1))
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;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty (null)))
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(imm ty 0))
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;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller
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;; Base case, simply adding things in registers.
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(rule (lower (has_type (fits_in_64 ty) (iadd x y)))
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(add ty x y))
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;; Special cases for when one operand is an immediate that fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_value y))))
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(add_imm ty x y))
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(rule (lower (has_type (fits_in_64 ty) (iadd (imm12_from_value x) y)))
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(add_imm ty y x))
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;; Same as the previous special cases, except we can switch the addition to a
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;; subtraction if the negated immediate fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_negated_value y))))
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(sub_imm ty x y))
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(rule (lower (has_type (fits_in_64 ty) (iadd (imm12_from_negated_value x) y)))
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(sub_imm ty y x))
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;; Special cases for when we're adding an extended register where the extending
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;; operation can get folded into the add itself.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (extended_value_from_value y))))
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(add_extend ty x y))
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(rule (lower (has_type (fits_in_64 ty) (iadd (extended_value_from_value x) y)))
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(add_extend ty y x))
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;; Special cases for when we're adding the shift of a different
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;; register by a constant amount and the shift can get folded into the add.
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(rule (lower (has_type (fits_in_64 ty)
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(iadd x (ishl y (iconst (lshl_from_imm64 <ty amt))))))
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(add_shift ty x y amt))
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(rule (lower (has_type (fits_in_64 ty)
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(iadd (ishl x (iconst (lshl_from_imm64 <ty amt))) y)))
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(add_shift ty y x amt))
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;; Fold an `iadd` and `imul` combination into a `madd` instruction.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (imul y z))))
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(madd ty y z x))
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(rule (lower (has_type (fits_in_64 ty) (iadd (imul x y) z)))
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(madd ty x y z))
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;; vectors
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(rule (lower (has_type ty @ (multi_lane _ _) (iadd x y)))
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(add_vec x y (vector_size ty)))
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;; `i128`
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(rule (lower (has_type $I128 (iadd x y)))
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(let
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;; Get the high/low registers for `x`.
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((x_regs ValueRegs x)
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs y)
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1)))
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;; the actual addition is `adds` followed by `adc` which comprises the
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;; low/high bits of the result
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(with_flags
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(add_with_flags_paired $I64 x_lo y_lo)
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(adc_paired $I64 x_hi y_hi))))
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;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller
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;; Base case, simply subtracting things in registers.
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(rule (lower (has_type (fits_in_64 ty) (isub x y)))
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(sub ty x y))
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;; Special case for when one operand is an immediate that fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (isub x (imm12_from_value y))))
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(sub_imm ty x y))
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;; Same as the previous special case, except we can switch the subtraction to an
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;; addition if the negated immediate fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (isub x (imm12_from_negated_value y))))
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(add_imm ty x y))
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;; Special cases for when we're subtracting an extended register where the
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;; extending operation can get folded into the sub itself.
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(rule (lower (has_type (fits_in_64 ty) (isub x (extended_value_from_value y))))
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(sub_extend ty x y))
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;; Finally a special case for when we're subtracting the shift of a different
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;; register by a constant amount and the shift can get folded into the sub.
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(rule (lower (has_type (fits_in_64 ty)
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(isub x (ishl y (iconst (lshl_from_imm64 <ty amt))))))
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(sub_shift ty x y amt))
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;; vectors
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(rule (lower (has_type ty @ (multi_lane _ _) (isub x y)))
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(sub_vec x y (vector_size ty)))
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;; `i128`
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(rule (lower (has_type $I128 (isub x y)))
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(let
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;; Get the high/low registers for `x`.
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((x_regs ValueRegs x)
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs y)
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1)))
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;; the actual subtraction is `subs` followed by `sbc` which comprises
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;; the low/high bits of the result
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(with_flags
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(sub_with_flags_paired $I64 x_lo y_lo)
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(sbc_paired $I64 x_hi y_hi))))
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;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (vec128 ty) (uadd_sat x y)))
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(uqadd x y (vector_size ty)))
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;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (vec128 ty) (sadd_sat x y)))
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(sqadd x y (vector_size ty)))
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;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (vec128 ty) (usub_sat x y)))
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(uqsub x y (vector_size ty)))
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;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (vec128 ty) (ssub_sat x y)))
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(sqsub x y (vector_size ty)))
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;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller.
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(rule (lower (has_type (fits_in_64 ty) (ineg x)))
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(sub ty (zero_reg) x))
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;; vectors.
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(rule (lower (has_type (vec128 ty) (ineg x)))
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(neg x (vector_size ty)))
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;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller.
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(rule (lower (has_type (fits_in_64 ty) (imul x y)))
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(madd ty x y (zero_reg)))
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;; `i128`.
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(rule (lower (has_type $I128 (imul x y)))
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(let
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;; Get the high/low registers for `x`.
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((x_regs ValueRegs x)
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs y)
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1))
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;; 128bit mul formula:
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;; dst_lo = x_lo * y_lo
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;; dst_hi = umulhi(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
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;;
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;; We can convert the above formula into the following
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;; umulh dst_hi, x_lo, y_lo
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;; madd dst_hi, x_lo, y_hi, dst_hi
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;; madd dst_hi, x_hi, y_lo, dst_hi
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;; madd dst_lo, x_lo, y_lo, zero
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(dst_hi1 Reg (umulh $I64 x_lo y_lo))
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(dst_hi2 Reg (madd64 x_lo y_hi dst_hi1))
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(dst_hi Reg (madd64 x_hi y_lo dst_hi2))
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(dst_lo Reg (madd64 x_lo y_lo (zero_reg))))
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(value_regs dst_lo dst_hi)))
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;; Case for i8x16, i16x8, and i32x4.
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(rule (lower (has_type (vec128 ty @ (not_i64x2)) (imul x y)))
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(mul x y (vector_size ty)))
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;; Special lowering for i64x2.
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;;
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;; This I64X2 multiplication is performed with several 32-bit
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;; operations.
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;;
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;; 64-bit numbers x and y, can be represented as:
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;; x = a + 2^32(b)
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;; y = c + 2^32(d)
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;;
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;; A 64-bit multiplication is:
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;; x * y = ac + 2^32(ad + bc) + 2^64(bd)
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;; note: `2^64(bd)` can be ignored, the value is too large to fit in
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;; 64 bits.
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;;
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;; This sequence implements a I64X2 multiply, where the registers
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;; `rn` and `rm` are split up into 32-bit components:
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;; rn = |d|c|b|a|
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;; rm = |h|g|f|e|
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;;
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;; rn * rm = |cg + 2^32(ch + dg)|ae + 2^32(af + be)|
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;;
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;; The sequence is:
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;; rev64 rd.4s, rm.4s
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;; mul rd.4s, rd.4s, rn.4s
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;; xtn tmp1.2s, rn.2d
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;; addp rd.4s, rd.4s, rd.4s
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;; xtn tmp2.2s, rm.2d
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;; shll rd.2d, rd.2s, #32
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;; umlal rd.2d, tmp2.2s, tmp1.2s
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(rule (lower (has_type $I64X2 (imul x y)))
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(let ((rn Reg x)
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(rm Reg y)
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;; Reverse the 32-bit elements in the 64-bit words.
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;; rd = |g|h|e|f|
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(rev Reg (rev64 rm (VectorSize.Size32x4)))
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;; Calculate the high half components.
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;; rd = |dg|ch|be|af|
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;;
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;; Note that this 32-bit multiply of the high half
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;; discards the bits that would overflow, same as
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;; if 64-bit operations were used. Also the Shll
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;; below would shift out the overflow bits anyway.
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(mul Reg (mul rev rn (VectorSize.Size32x4)))
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;; Extract the low half components of rn.
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;; tmp1 = |c|a|
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(tmp1 Reg (xtn64 rn $false))
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;; Sum the respective high half components.
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;; rd = |dg+ch|be+af||dg+ch|be+af|
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(sum Reg (addp mul mul (VectorSize.Size32x4)))
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;; Extract the low half components of rm.
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;; tmp2 = |g|e|
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(tmp2 Reg (xtn64 rm $false))
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;; Shift the high half components, into the high half.
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;; rd = |dg+ch << 32|be+af << 32|
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(shift Reg (shll32 sum $false))
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;; Multiply the low components together, and accumulate with the high
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;; half.
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;; rd = |rd[1] + cg|rd[0] + ae|
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(result Reg (umlal32 shift tmp2 tmp1 $false)))
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result))
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;; Special case for `i16x8.extmul_low_i8x16_s`.
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(rule (lower (has_type $I16X8
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(imul (swiden_low x @ (value_type $I8X16))
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(swiden_low y @ (value_type $I8X16)))))
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(smull8 x y $false))
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;; Special case for `i16x8.extmul_high_i8x16_s`.
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(rule (lower (has_type $I16X8
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(imul (swiden_high x @ (value_type $I8X16))
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(swiden_high y @ (value_type $I8X16)))))
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(smull8 x y $true))
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;; Special case for `i16x8.extmul_low_i8x16_u`.
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(rule (lower (has_type $I16X8
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(imul (uwiden_low x @ (value_type $I8X16))
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(uwiden_low y @ (value_type $I8X16)))))
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(umull8 x y $false))
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;; Special case for `i16x8.extmul_high_i8x16_u`.
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(rule (lower (has_type $I16X8
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(imul (uwiden_high x @ (value_type $I8X16))
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(uwiden_high y @ (value_type $I8X16)))))
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(umull8 x y $true))
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;; Special case for `i32x4.extmul_low_i16x8_s`.
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(rule (lower (has_type $I32X4
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(imul (swiden_low x @ (value_type $I16X8))
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(swiden_low y @ (value_type $I16X8)))))
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(smull16 x y $false))
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;; Special case for `i32x4.extmul_high_i16x8_s`.
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(rule (lower (has_type $I32X4
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(imul (swiden_high x @ (value_type $I16X8))
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(swiden_high y @ (value_type $I16X8)))))
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(smull16 x y $true))
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;; Special case for `i32x4.extmul_low_i16x8_u`.
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(rule (lower (has_type $I32X4
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(imul (uwiden_low x @ (value_type $I16X8))
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(uwiden_low y @ (value_type $I16X8)))))
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(umull16 x y $false))
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;; Special case for `i32x4.extmul_high_i16x8_u`.
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(rule (lower (has_type $I32X4
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(imul (uwiden_high x @ (value_type $I16X8))
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(uwiden_high y @ (value_type $I16X8)))))
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(umull16 x y $true))
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;; Special case for `i64x2.extmul_low_i32x4_s`.
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(rule (lower (has_type $I64X2
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(imul (swiden_low x @ (value_type $I32X4))
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(swiden_low y @ (value_type $I32X4)))))
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(smull32 x y $false))
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;; Special case for `i64x2.extmul_high_i32x4_s`.
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(rule (lower (has_type $I64X2
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(imul (swiden_high x @ (value_type $I32X4))
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(swiden_high y @ (value_type $I32X4)))))
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(smull32 x y $true))
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;; Special case for `i64x2.extmul_low_i32x4_u`.
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(rule (lower (has_type $I64X2
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(imul (uwiden_low x @ (value_type $I32X4))
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(uwiden_low y @ (value_type $I32X4)))))
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(umull32 x y $false))
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;; Special case for `i64x2.extmul_high_i32x4_u`.
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(rule (lower (has_type $I64X2
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(imul (uwiden_high x @ (value_type $I32X4))
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(uwiden_high y @ (value_type $I32X4)))))
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(umull32 x y $true))
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;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type $I64 (smulhi x y)))
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(smulh $I64 x y))
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(rule (lower (has_type (fits_in_32 ty) (smulhi x y)))
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(let ((x64 Reg (put_in_reg_sext64 x))
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(y64 Reg (put_in_reg_sext64 y))
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(mul Reg (madd64 x64 y64 (zero_reg)))
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(result Reg (asr_imm $I64 mul (imm_shift_from_u8 (ty_bits ty)))))
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result))
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;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type $I64 (umulhi x y)))
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(umulh $I64 x y))
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(rule (lower (has_type (fits_in_32 ty) (umulhi x y)))
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(let ((x64 Reg (put_in_reg_zext64 x))
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(y64 Reg (put_in_reg_zext64 y))
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(mul Reg (madd64 x64 y64 (zero_reg)))
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(result Reg (lsr_imm $I64 mul (imm_shift_from_u8 (ty_bits ty)))))
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result))
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;;;; Rules for `udiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO: Add UDiv32 to implement 32-bit directly, rather
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;; than extending the input.
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;;
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;; Note that aarch64's `udiv` doesn't trap so to respect the semantics of
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;; CLIF's `udiv` the check for zero needs to be manually performed.
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(rule (lower (has_type (fits_in_64 ty) (udiv x y)))
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(a64_udiv $I64 (put_in_reg_zext64 x) (put_nonzero_in_reg_zext64 y)))
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;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
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(decl put_nonzero_in_reg_zext64 (Value) Reg)
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(rule (put_nonzero_in_reg_zext64 val)
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(trap_if_zero_divisor (put_in_reg_zext64 val)))
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;; Special case where if a `Value` is known to be nonzero we can trivially
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;; move it into a register.
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(rule (put_nonzero_in_reg_zext64 (and (value_type ty)
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(iconst (nonzero_u64_from_imm64 n))))
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(imm ty n))
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;;;; Rules for `sdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; TODO: Add SDiv32 to implement 32-bit directly, rather
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;; than extending the input.
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;;
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;; The sequence of checks here should look like:
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;;
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;; cbnz rm, #8
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;; udf ; divide by zero
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;; cmn rm, 1
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;; ccmp rn, 1, #nzcv, eq
|
|
;; b.vc #8
|
|
;; udf ; signed overflow
|
|
;;
|
|
;; Note The div instruction does not trap on divide by zero or overflow, so
|
|
;; checks need to be manually inserted.
|
|
;;
|
|
;; TODO: if `y` is -1 then a check that `x` is not INT_MIN is all that's
|
|
;; necessary, but right now `y` is checked to not be -1 as well.
|
|
(rule (lower (has_type (fits_in_64 ty) (sdiv x y)))
|
|
(let ((x64 Reg (put_in_reg_sext64 x))
|
|
(y64 Reg (put_nonzero_in_reg_sext64 y))
|
|
(valid_x64 Reg (trap_if_div_overflow ty x64 y64))
|
|
(result Reg (a64_sdiv $I64 valid_x64 y64)))
|
|
result))
|
|
|
|
;; Helper for extracting an immediate that's not 0 and not -1 from an imm64.
|
|
(decl safe_divisor_from_imm64 (u64) Imm64)
|
|
(extern extractor safe_divisor_from_imm64 safe_divisor_from_imm64)
|
|
|
|
;; Special case for `sdiv` where no checks are needed due to division by a
|
|
;; constant meaning the checks are always passed.
|
|
(rule (lower (has_type (fits_in_64 ty) (sdiv x (iconst (safe_divisor_from_imm64 y)))))
|
|
(a64_sdiv $I64 (put_in_reg_sext64 x) (imm ty y)))
|
|
|
|
;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
|
|
(decl put_nonzero_in_reg_sext64 (Value) Reg)
|
|
(rule (put_nonzero_in_reg_sext64 val)
|
|
(trap_if_zero_divisor (put_in_reg_sext64 val)))
|
|
|
|
;; Note that this has a special case where if the `Value` is a constant that's
|
|
;; not zero we can skip the zero check.
|
|
(rule (put_nonzero_in_reg_sext64 (and (value_type ty)
|
|
(iconst (nonzero_u64_from_imm64 n))))
|
|
(imm ty n))
|
|
|
|
;;;; Rules for `urem` and `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; Remainder (x % y) is implemented as:
|
|
;;
|
|
;; tmp = x / y
|
|
;; result = x - (tmp*y)
|
|
;;
|
|
;; use 'result' for tmp and you have:
|
|
;;
|
|
;; cbnz y, #8 ; branch over trap
|
|
;; udf ; divide by zero
|
|
;; div rd, x, y ; rd = x / y
|
|
;; msub rd, rd, y, x ; rd = x - rd * y
|
|
|
|
(rule (lower (has_type (fits_in_64 ty) (urem x y)))
|
|
(let ((x64 Reg (put_in_reg_zext64 x))
|
|
(y64 Reg (put_nonzero_in_reg_zext64 y))
|
|
(div Reg (a64_udiv $I64 x64 y64))
|
|
(result Reg (msub64 div y64 x64)))
|
|
result))
|
|
|
|
(rule (lower (has_type (fits_in_64 ty) (srem x y)))
|
|
(let ((x64 Reg (put_in_reg_sext64 x))
|
|
(y64 Reg (put_nonzero_in_reg_sext64 y))
|
|
(div Reg (a64_sdiv $I64 x64 y64))
|
|
(result Reg (msub64 div y64 x64)))
|
|
result))
|
|
|
|
;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; General rule for extending input to an output which fits in a single
|
|
;; register.
|
|
(rule (lower (has_type (fits_in_64 out) (uextend x @ (value_type in))))
|
|
(extend x $false (ty_bits in) (ty_bits out)))
|
|
|
|
;; Extraction of a vector lane automatically extends as necessary, so we can
|
|
;; skip an explicit extending instruction.
|
|
(rule (lower (has_type (fits_in_64 out)
|
|
(uextend (extractlane vec @ (value_type in)
|
|
(u8_from_uimm8 lane)))))
|
|
(mov_from_vec (put_in_reg vec) lane (vector_size in)))
|
|
|
|
;; Atomic loads will also automatically zero their upper bits so the `uextend`
|
|
;; instruction can effectively get skipped here.
|
|
(rule (lower (has_type (fits_in_64 out)
|
|
(uextend (and (value_type in) (sinkable_atomic_load addr)))))
|
|
(load_acquire in (sink_atomic_load addr)))
|
|
|
|
;; Conversion to 128-bit needs a zero-extension of the lower bits and the upper
|
|
;; bits are all zero.
|
|
(rule (lower (has_type $I128 (uextend x)))
|
|
(value_regs (put_in_reg_zext64 x) (imm $I64 0)))
|
|
|
|
;; Like above where vector extraction automatically zero-extends extending to
|
|
;; i128 only requires generating a 0 constant for the upper bits.
|
|
(rule (lower (has_type $I128
|
|
(uextend (extractlane vec @ (value_type in)
|
|
(u8_from_uimm8 lane)))))
|
|
(value_regs (mov_from_vec (put_in_reg vec) lane (vector_size in)) (imm $I64 0)))
|
|
|
|
;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; General rule for extending input to an output which fits in a single
|
|
;; register.
|
|
(rule (lower (has_type (fits_in_64 out) (sextend x @ (value_type in))))
|
|
(extend x $true (ty_bits in) (ty_bits out)))
|
|
|
|
;; Extraction of a vector lane automatically extends as necessary, so we can
|
|
;; skip an explicit extending instruction.
|
|
(rule (lower (has_type (fits_in_64 out)
|
|
(sextend (extractlane vec @ (value_type in)
|
|
(u8_from_uimm8 lane)))))
|
|
(mov_from_vec_signed (put_in_reg vec)
|
|
lane
|
|
(vector_size in)
|
|
(size_from_ty out)))
|
|
|
|
;; 64-bit to 128-bit only needs to sign-extend the input to the upper bits.
|
|
(rule (lower (has_type $I128 (sextend x)))
|
|
(let ((lo Reg (put_in_reg_sext64 x))
|
|
(hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
|
|
(value_regs lo hi)))
|
|
|
|
;; Like above where vector extraction automatically zero-extends extending to
|
|
;; i128 only requires generating a 0 constant for the upper bits.
|
|
;;
|
|
;; Note that `mov_from_vec_signed` doesn't exist for i64x2, so that's
|
|
;; specifically excluded here.
|
|
(rule (lower (has_type $I128
|
|
(sextend (extractlane vec @ (value_type in @ (not_i64x2))
|
|
(u8_from_uimm8 lane)))))
|
|
(let ((lo Reg (mov_from_vec_signed (put_in_reg vec)
|
|
lane
|
|
(vector_size in)
|
|
(size_from_ty $I64)))
|
|
(hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
|
|
(value_regs lo hi)))
|
|
|
|
;; Extension from an extraction of i64x2 into i128.
|
|
(rule (lower (has_type $I128
|
|
(sextend (extractlane vec @ (value_type $I64X2)
|
|
(u8_from_uimm8 lane)))))
|
|
(let ((lo Reg (mov_from_vec (put_in_reg vec)
|
|
lane
|
|
(VectorSize.Size64x2)))
|
|
(hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
|
|
(value_regs lo hi)))
|
|
|
|
;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; Base case using `orn` between two registers.
|
|
;;
|
|
;; Note that bitwise negation is implemented here as
|
|
;;
|
|
;; NOT rd, rm ==> ORR_NOT rd, zero, rm
|
|
(rule (lower (has_type (fits_in_64 ty) (bnot x)))
|
|
(orr_not ty (zero_reg) x))
|
|
|
|
;; Special case to use `orr_not_shift` if it's a `bnot` of a const-left-shifted
|
|
;; value.
|
|
(rule (lower (has_type (fits_in_64 ty)
|
|
(bnot (ishl x (iconst (lshl_from_imm64 <ty amt))))))
|
|
(orr_not_shift ty (zero_reg) x amt))
|
|
|
|
;; Implementation of `bnot` for `i128`.
|
|
(rule (lower (has_type $I128 (bnot x)))
|
|
(let ((x_regs ValueRegs x)
|
|
(x_lo Reg (value_regs_get x_regs 0))
|
|
(x_hi Reg (value_regs_get x_regs 1))
|
|
(new_lo Reg (orr_not $I64 (zero_reg) x_lo))
|
|
(new_hi Reg (orr_not $I64 (zero_reg) x_hi)))
|
|
(value_regs new_lo new_hi)))
|
|
|
|
;; Implementation of `bnot` for vector types.
|
|
(rule (lower (has_type (vec128 ty) (bnot x)))
|
|
(not x (vector_size ty)))
|
|
|
|
;;;; Rules for `band` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
(rule (lower (has_type (fits_in_32 ty) (band x y)))
|
|
(alu_rs_imm_logic_commutative (ALUOp.And) ty x y))
|
|
|
|
(rule (lower (has_type $I64 (band x y)))
|
|
(alu_rs_imm_logic_commutative (ALUOp.And) $I64 x y))
|
|
|
|
(rule (lower (has_type $I128 (band x y))) (i128_alu_bitop (ALUOp.And) $I64 x y))
|
|
|
|
(rule (lower (has_type (vec128 ty) (band x y)))
|
|
(and_vec x y (vector_size ty)))
|
|
|
|
;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
(rule (lower (has_type (fits_in_32 ty) (bor x y)))
|
|
(alu_rs_imm_logic_commutative (ALUOp.Orr) ty x y))
|
|
|
|
(rule (lower (has_type $I64 (bor x y)))
|
|
(alu_rs_imm_logic_commutative (ALUOp.Orr) $I64 x y))
|
|
|
|
(rule (lower (has_type $I128 (bor x y))) (i128_alu_bitop (ALUOp.Orr) $I64 x y))
|
|
|
|
(rule (lower (has_type (vec128 ty) (bor x y)))
|
|
(orr_vec x y (vector_size ty)))
|
|
|
|
;;;; Rules for `bxor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
(rule (lower (has_type (fits_in_32 ty) (bxor x y)))
|
|
(alu_rs_imm_logic_commutative (ALUOp.Eor) ty x y))
|
|
|
|
(rule (lower (has_type $I64 (bxor x y)))
|
|
(alu_rs_imm_logic_commutative (ALUOp.Eor) $I64 x y))
|
|
|
|
(rule (lower (has_type $I128 (bxor x y))) (i128_alu_bitop (ALUOp.Eor) $I64 x y))
|
|
|
|
(rule (lower (has_type (vec128 ty) (bxor x y)))
|
|
(eor_vec x y (vector_size ty)))
|
|
|
|
;;;; Rules for `band_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
(rule (lower (has_type (fits_in_32 ty) (band_not x y)))
|
|
(alu_rs_imm_logic (ALUOp.AndNot) ty x y))
|
|
|
|
(rule (lower (has_type $I64 (band_not x y)))
|
|
(alu_rs_imm_logic (ALUOp.AndNot) $I64 x y))
|
|
|
|
(rule (lower (has_type $I128 (band_not x y))) (i128_alu_bitop (ALUOp.AndNot) $I64 x y))
|
|
|
|
(rule (lower (has_type (vec128 ty) (band_not x y)))
|
|
(bic_vec x y (vector_size ty)))
|
|
|
|
;;;; Rules for `bor_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
(rule (lower (has_type (fits_in_32 ty) (bor_not x y)))
|
|
(alu_rs_imm_logic (ALUOp.OrrNot) ty x y))
|
|
|
|
(rule (lower (has_type $I64 (bor_not x y)))
|
|
(alu_rs_imm_logic (ALUOp.OrrNot) $I64 x y))
|
|
|
|
(rule (lower (has_type $I128 (bor_not x y))) (i128_alu_bitop (ALUOp.OrrNot) $I64 x y))
|
|
|
|
;;;; Rules for `bxor_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
(rule (lower (has_type (fits_in_32 ty) (bxor_not x y)))
|
|
(alu_rs_imm_logic (ALUOp.EorNot) $I32 x y))
|
|
|
|
(rule (lower (has_type $I64 (bxor_not x y)))
|
|
(alu_rs_imm_logic (ALUOp.EorNot) $I64 x y))
|
|
|
|
(rule (lower (has_type $I128 (bxor_not x y))) (i128_alu_bitop (ALUOp.EorNot) $I64 x y))
|
|
|
|
;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; Shift for i8/i16/i32.
|
|
(rule (lower (has_type (fits_in_32 ty) (ishl x y)))
|
|
(do_shift (ALUOp.Lsl) ty x y))
|
|
|
|
;; Shift for i64.
|
|
(rule (lower (has_type $I64 (ishl x y)))
|
|
(do_shift (ALUOp.Lsl) $I64 x y))
|
|
|
|
;; Shift for i128.
|
|
(rule (lower (has_type $I128 (ishl x y)))
|
|
(lower_shl128 x (value_regs_get y 0)))
|
|
|
|
;; lsl lo_lshift, src_lo, amt
|
|
;; lsl hi_lshift, src_hi, amt
|
|
;; mvn inv_amt, amt
|
|
;; lsr lo_rshift, src_lo, #1
|
|
;; lsr lo_rshift, lo_rshift, inv_amt
|
|
;; orr maybe_hi, hi_lshift, lo_rshift
|
|
;; tst amt, #0x40
|
|
;; csel dst_hi, lo_lshift, maybe_hi, ne
|
|
;; csel dst_lo, xzr, lo_lshift, ne
|
|
(decl lower_shl128 (ValueRegs Reg) ValueRegs)
|
|
(rule (lower_shl128 src amt)
|
|
(let ((src_lo Reg (value_regs_get src 0))
|
|
(src_hi Reg (value_regs_get src 1))
|
|
(lo_lshift Reg (lsl $I64 src_lo amt))
|
|
(hi_lshift Reg (lsl $I64 src_hi amt))
|
|
(inv_amt Reg (orr_not $I32 (zero_reg) amt))
|
|
(lo_rshift Reg (lsr $I64 (lsr_imm $I64 src_lo (imm_shift_from_u8 1))
|
|
inv_amt))
|
|
(maybe_hi Reg (orr $I64 hi_lshift lo_rshift))
|
|
)
|
|
(with_flags
|
|
(tst_imm $I64 amt (u64_into_imm_logic $I64 64))
|
|
(consumes_flags_concat
|
|
(csel (Cond.Ne) (zero_reg) lo_lshift)
|
|
(csel (Cond.Ne) lo_lshift maybe_hi)))))
|
|
|
|
;; Shift for vector types.
|
|
(rule (lower (has_type (vec128 ty) (ishl x y)))
|
|
(let ((size VectorSize (vector_size ty))
|
|
(shift Reg (vec_dup y size)))
|
|
(sshl x shift size)))
|
|
|
|
;; Helper function to emit a shift operation with the opcode specified and
|
|
;; the output type specified. The `Reg` provided is shifted by the `Value`
|
|
;; given.
|
|
;;
|
|
;; Note that this automatically handles the clif semantics of masking the
|
|
;; shift amount where necessary.
|
|
(decl do_shift (ALUOp Type Reg Value) Reg)
|
|
|
|
;; 8/16-bit shift base case.
|
|
;;
|
|
;; When shifting for amounts larger than the size of the type, the CLIF shift
|
|
;; instructions implement a "wrapping" behaviour, such that an i8 << 8 is
|
|
;; equivalent to i8 << 0
|
|
;;
|
|
;; On i32 and i64 types this matches what the aarch64 spec does, but on smaller
|
|
;; types (i16, i8) we need to do this manually, so we wrap the shift amount
|
|
;; with an AND instruction
|
|
(rule (do_shift op (fits_in_16 ty) x y)
|
|
(let ((shift_amt Reg (value_regs_get y 0))
|
|
(masked_shift_amt Reg (and_imm $I32 shift_amt (shift_mask ty))))
|
|
(alu_rrr op $I32 x masked_shift_amt)))
|
|
|
|
(decl shift_mask (Type) ImmLogic)
|
|
(extern constructor shift_mask shift_mask)
|
|
|
|
;; 32/64-bit shift base cases.
|
|
(rule (do_shift op $I32 x y) (alu_rrr op $I32 x (value_regs_get y 0)))
|
|
(rule (do_shift op $I64 x y) (alu_rrr op $I64 x (value_regs_get y 0)))
|
|
|
|
;; Special case for shifting by a constant value where the value can fit into an
|
|
;; `ImmShift`.
|
|
;;
|
|
;; Note that this rule explicitly has a higher priority than the others
|
|
;; to ensure it's attempted first, otherwise the type-based filters on the
|
|
;; previous rules seem to take priority over this rule.
|
|
(rule 1 (do_shift op ty x (iconst (imm_shift_from_imm64 <ty shift)))
|
|
(alu_rr_imm_shift op ty x shift))
|
|
|
|
;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; Shift for i8/i16/i32.
|
|
(rule (lower (has_type (fits_in_32 ty) (ushr x y)))
|
|
(do_shift (ALUOp.Lsr) ty (put_in_reg_zext32 x) y))
|
|
|
|
;; Shift for i64.
|
|
(rule (lower (has_type $I64 (ushr x y)))
|
|
(do_shift (ALUOp.Lsr) $I64 (put_in_reg_zext64 x) y))
|
|
|
|
;; Shift for i128.
|
|
(rule (lower (has_type $I128 (ushr x y)))
|
|
(lower_ushr128 x (value_regs_get y 0)))
|
|
|
|
;; Vector shifts.
|
|
(rule (lower (has_type (vec128 ty) (ushr x y)))
|
|
(let ((size VectorSize (vector_size ty))
|
|
(shift Reg (vec_dup (sub $I32 (zero_reg) y) size)))
|
|
(ushl x shift size)))
|
|
|
|
;; lsr lo_rshift, src_lo, amt
|
|
;; lsr hi_rshift, src_hi, amt
|
|
;; mvn inv_amt, amt
|
|
;; lsl hi_lshift, src_hi, #1
|
|
;; lsl hi_lshift, hi_lshift, inv_amt
|
|
;; tst amt, #0x40
|
|
;; orr maybe_lo, lo_rshift, hi_lshift
|
|
;; csel dst_hi, xzr, hi_rshift, ne
|
|
;; csel dst_lo, hi_rshift, maybe_lo, ne
|
|
(decl lower_ushr128 (ValueRegs Reg) ValueRegs)
|
|
(rule (lower_ushr128 src amt)
|
|
(let ((src_lo Reg (value_regs_get src 0))
|
|
(src_hi Reg (value_regs_get src 1))
|
|
(lo_rshift Reg (lsr $I64 src_lo amt))
|
|
(hi_rshift Reg (lsr $I64 src_hi amt))
|
|
|
|
(inv_amt Reg (orr_not $I32 (zero_reg) amt))
|
|
(hi_lshift Reg (lsl $I64 (lsl_imm $I64 src_hi (imm_shift_from_u8 1))
|
|
inv_amt))
|
|
(maybe_lo Reg (orr $I64 lo_rshift hi_lshift))
|
|
)
|
|
(with_flags
|
|
(tst_imm $I64 amt (u64_into_imm_logic $I64 64))
|
|
(consumes_flags_concat
|
|
(csel (Cond.Ne) hi_rshift maybe_lo)
|
|
(csel (Cond.Ne) (zero_reg) hi_rshift)))))
|
|
|
|
;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; Shift for i8/i16/i32.
|
|
(rule (lower (has_type (fits_in_32 ty) (sshr x y)))
|
|
(do_shift (ALUOp.Asr) ty (put_in_reg_sext32 x) y))
|
|
|
|
;; Shift for i64.
|
|
(rule (lower (has_type $I64 (sshr x y)))
|
|
(do_shift (ALUOp.Asr) $I64 (put_in_reg_sext64 x) y))
|
|
|
|
;; Shift for i128.
|
|
(rule (lower (has_type $I128 (sshr x y)))
|
|
(lower_sshr128 x (value_regs_get y 0)))
|
|
|
|
;; Vector shifts.
|
|
;;
|
|
;; Note that right shifts are implemented with a negative left shift.
|
|
(rule (lower (has_type (vec128 ty) (sshr x y)))
|
|
(let ((size VectorSize (vector_size ty))
|
|
(shift Reg (vec_dup (sub $I32 (zero_reg) y) size)))
|
|
(sshl x shift size)))
|
|
|
|
;; lsr lo_rshift, src_lo, amt
|
|
;; asr hi_rshift, src_hi, amt
|
|
;; mvn inv_amt, amt
|
|
;; lsl hi_lshift, src_hi, #1
|
|
;; lsl hi_lshift, hi_lshift, inv_amt
|
|
;; asr hi_sign, src_hi, #63
|
|
;; orr maybe_lo, lo_rshift, hi_lshift
|
|
;; tst amt, #0x40
|
|
;; csel dst_hi, hi_sign, hi_rshift, ne
|
|
;; csel dst_lo, hi_rshift, maybe_lo, ne
|
|
(decl lower_sshr128 (ValueRegs Reg) ValueRegs)
|
|
(rule (lower_sshr128 src amt)
|
|
(let ((src_lo Reg (value_regs_get src 0))
|
|
(src_hi Reg (value_regs_get src 1))
|
|
(lo_rshift Reg (lsr $I64 src_lo amt))
|
|
(hi_rshift Reg (asr $I64 src_hi amt))
|
|
|
|
(inv_amt Reg (orr_not $I32 (zero_reg) amt))
|
|
(hi_lshift Reg (lsl $I64 (lsl_imm $I64 src_hi (imm_shift_from_u8 1))
|
|
inv_amt))
|
|
(hi_sign Reg (asr_imm $I64 src_hi (imm_shift_from_u8 63)))
|
|
(maybe_lo Reg (orr $I64 lo_rshift hi_lshift))
|
|
)
|
|
(with_flags
|
|
(tst_imm $I64 amt (u64_into_imm_logic $I64 64))
|
|
(consumes_flags_concat
|
|
(csel (Cond.Ne) hi_rshift maybe_lo)
|
|
(csel (Cond.Ne) hi_sign hi_rshift)))))
|
|
|
|
;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; General 8/16-bit case.
|
|
(rule (lower (has_type (fits_in_16 ty) (rotl x y)))
|
|
(let ((neg_shift Reg (sub $I32 (zero_reg) y)))
|
|
(small_rotr ty (put_in_reg_zext32 x) neg_shift)))
|
|
|
|
;; Specialization for the 8/16-bit case when the rotation amount is an immediate.
|
|
(rule (lower (has_type (fits_in_16 ty) (rotl x (iconst (imm_shift_from_imm64 <ty n)))))
|
|
(small_rotr_imm ty (put_in_reg_zext32 x) (negate_imm_shift ty n)))
|
|
|
|
;; aarch64 doesn't have a left-rotate instruction, but a left rotation of K
|
|
;; places is effectively a right rotation of N - K places, if N is the integer's
|
|
;; bit size. We implement left rotations with this trick.
|
|
;;
|
|
;; Note that when negating the shift amount here the upper bits are ignored
|
|
;; by the rotr instruction, meaning that we'll still left-shift by the desired
|
|
;; amount.
|
|
|
|
;; General 32-bit case.
|
|
(rule (lower (has_type $I32 (rotl x y)))
|
|
(let ((neg_shift Reg (sub $I32 (zero_reg) y)))
|
|
(a64_rotr $I32 x neg_shift)))
|
|
|
|
;; General 64-bit case.
|
|
(rule (lower (has_type $I64 (rotl x y)))
|
|
(let ((neg_shift Reg (sub $I64 (zero_reg) y)))
|
|
(a64_rotr $I64 x neg_shift)))
|
|
|
|
;; Specialization for the 32-bit case when the rotation amount is an immediate.
|
|
(rule (lower (has_type $I32 (rotl x (iconst (imm_shift_from_imm64 <$I32 n)))))
|
|
(a64_rotr_imm $I32 x (negate_imm_shift $I32 n)))
|
|
|
|
;; Specialization for the 64-bit case when the rotation amount is an immediate.
|
|
(rule (lower (has_type $I64 (rotl x (iconst (imm_shift_from_imm64 <$I64 n)))))
|
|
(a64_rotr_imm $I64 x (negate_imm_shift $I64 n)))
|
|
|
|
(decl negate_imm_shift (Type ImmShift) ImmShift)
|
|
(extern constructor negate_imm_shift negate_imm_shift)
|
|
|
|
;; General 128-bit case.
|
|
;;
|
|
;; TODO: much better codegen is possible with a constant amount.
|
|
(rule (lower (has_type $I128 (rotl x y)))
|
|
(let ((val ValueRegs x)
|
|
(amt Reg (value_regs_get y 0))
|
|
(neg_amt Reg (sub $I64 (imm $I64 128) amt))
|
|
(lshift ValueRegs (lower_shl128 val amt))
|
|
(rshift ValueRegs (lower_ushr128 val neg_amt)))
|
|
(value_regs
|
|
(orr $I64 (value_regs_get lshift 0) (value_regs_get rshift 0))
|
|
(orr $I64 (value_regs_get lshift 1) (value_regs_get rshift 1)))))
|
|
|
|
;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; General 8/16-bit case.
|
|
(rule (lower (has_type (fits_in_16 ty) (rotr x y)))
|
|
(small_rotr ty (put_in_reg_zext32 x) y))
|
|
|
|
;; General 32-bit case.
|
|
(rule (lower (has_type $I32 (rotr x y)))
|
|
(a64_rotr $I32 x y))
|
|
|
|
;; General 64-bit case.
|
|
(rule (lower (has_type $I64 (rotr x y)))
|
|
(a64_rotr $I64 x y))
|
|
|
|
;; Specialization for the 8/16-bit case when the rotation amount is an immediate.
|
|
(rule (lower (has_type (fits_in_16 ty) (rotr x (iconst (imm_shift_from_imm64 <ty n)))))
|
|
(small_rotr_imm ty (put_in_reg_zext32 x) n))
|
|
|
|
;; Specialization for the 32-bit case when the rotation amount is an immediate.
|
|
(rule (lower (has_type $I32 (rotr x (iconst (imm_shift_from_imm64 <$I32 n)))))
|
|
(a64_rotr_imm $I32 x n))
|
|
|
|
;; Specialization for the 64-bit case when the rotation amount is an immediate.
|
|
(rule (lower (has_type $I64 (rotr x (iconst (imm_shift_from_imm64 <$I64 n)))))
|
|
(a64_rotr_imm $I64 x n))
|
|
|
|
;; For a < 32-bit rotate-right, we synthesize this as:
|
|
;;
|
|
;; rotr rd, val, amt
|
|
;;
|
|
;; =>
|
|
;;
|
|
;; and masked_amt, amt, <bitwidth - 1>
|
|
;; sub tmp_sub, masked_amt, <bitwidth>
|
|
;; sub neg_amt, zero, tmp_sub ; neg
|
|
;; lsr val_rshift, val, masked_amt
|
|
;; lsl val_lshift, val, neg_amt
|
|
;; orr rd, val_lshift val_rshift
|
|
(decl small_rotr (Type Reg Reg) Reg)
|
|
(rule (small_rotr ty val amt)
|
|
(let ((masked_amt Reg (and_imm $I32 amt (rotr_mask ty)))
|
|
(tmp_sub Reg (sub_imm $I32 masked_amt (u8_into_imm12 (ty_bits ty))))
|
|
(neg_amt Reg (sub $I32 (zero_reg) tmp_sub))
|
|
(val_rshift Reg (lsr $I32 val masked_amt))
|
|
(val_lshift Reg (lsl $I32 val neg_amt)))
|
|
(orr $I32 val_lshift val_rshift)))
|
|
|
|
(decl rotr_mask (Type) ImmLogic)
|
|
(extern constructor rotr_mask rotr_mask)
|
|
|
|
;; For a constant amount, we can instead do:
|
|
;;
|
|
;; rotr rd, val, #amt
|
|
;;
|
|
;; =>
|
|
;;
|
|
;; lsr val_rshift, val, #<amt>
|
|
;; lsl val_lshift, val, <bitwidth - amt>
|
|
;; orr rd, val_lshift, val_rshift
|
|
(decl small_rotr_imm (Type Reg ImmShift) Reg)
|
|
(rule (small_rotr_imm ty val amt)
|
|
(let ((val_rshift Reg (lsr_imm $I32 val amt))
|
|
(val_lshift Reg (lsl_imm $I32 val (rotr_opposite_amount ty amt))))
|
|
(orr $I32 val_lshift val_rshift)))
|
|
|
|
(decl rotr_opposite_amount (Type ImmShift) ImmShift)
|
|
(extern constructor rotr_opposite_amount rotr_opposite_amount)
|
|
|
|
;; General 128-bit case.
|
|
;;
|
|
;; TODO: much better codegen is possible with a constant amount.
|
|
(rule (lower (has_type $I128 (rotr x y)))
|
|
(let ((val ValueRegs x)
|
|
(amt Reg (value_regs_get y 0))
|
|
(neg_amt Reg (sub $I64 (imm $I64 128) amt))
|
|
(rshift ValueRegs (lower_ushr128 val amt))
|
|
(lshift ValueRegs (lower_shl128 val neg_amt))
|
|
(hi Reg (orr $I64 (value_regs_get rshift 1) (value_regs_get lshift 1)))
|
|
(lo Reg (orr $I64 (value_regs_get rshift 0) (value_regs_get lshift 0))))
|
|
(value_regs lo hi)))
|
|
|
|
;;;; Rules for `bitrev` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; Reversing an 8-bit value with a 32-bit bitrev instruction will place
|
|
;; the reversed result in the highest 8 bits, so we need to shift them down into
|
|
;; place.
|
|
(rule (lower (has_type $I8 (bitrev x)))
|
|
(lsr_imm $I32 (rbit $I32 x) (imm_shift_from_u8 24)))
|
|
|
|
;; Reversing an 16-bit value with a 32-bit bitrev instruction will place
|
|
;; the reversed result in the highest 16 bits, so we need to shift them down into
|
|
;; place.
|
|
(rule (lower (has_type $I16 (bitrev x)))
|
|
(lsr_imm $I32 (rbit $I32 x) (imm_shift_from_u8 16)))
|
|
|
|
(rule (lower (has_type $I128 (bitrev x)))
|
|
(let ((val ValueRegs x)
|
|
(lo_rev Reg (rbit $I64 (value_regs_get val 0)))
|
|
(hi_rev Reg (rbit $I64 (value_regs_get val 1))))
|
|
(value_regs hi_rev lo_rev)))
|
|
|
|
(rule (lower (has_type ty (bitrev x)))
|
|
(rbit ty x))
|
|
|
|
|
|
;;;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
(rule (lower (has_type $I8 (clz x)))
|
|
(sub_imm $I32 (a64_clz $I32 (put_in_reg_zext32 x)) (u8_into_imm12 24)))
|
|
|
|
(rule (lower (has_type $I16 (clz x)))
|
|
(sub_imm $I32 (a64_clz $I32 (put_in_reg_zext32 x)) (u8_into_imm12 16)))
|
|
|
|
(rule (lower (has_type $I128 (clz x)))
|
|
(lower_clz128 x))
|
|
|
|
(rule (lower (has_type ty (clz x)))
|
|
(a64_clz ty x))
|
|
|
|
;; clz hi_clz, hi
|
|
;; clz lo_clz, lo
|
|
;; lsr tmp, hi_clz, #6
|
|
;; madd dst_lo, lo_clz, tmp, hi_clz
|
|
;; mov dst_hi, 0
|
|
(decl lower_clz128 (ValueRegs) ValueRegs)
|
|
(rule (lower_clz128 val)
|
|
(let ((hi_clz Reg (a64_clz $I64 (value_regs_get val 1)))
|
|
(lo_clz Reg (a64_clz $I64 (value_regs_get val 0)))
|
|
(tmp Reg (lsr_imm $I64 hi_clz (imm_shift_from_u8 6))))
|
|
(value_regs (madd64 lo_clz tmp hi_clz) (imm $I64 0))))
|
|
|
|
;;;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; Note that all `ctz` instructions are implemented by reversing the bits and
|
|
;; then using a `clz` instruction since the tail zeros are the same as the
|
|
;; leading zeros of the reversed value.
|
|
|
|
(rule (lower (has_type $I8 (ctz x)))
|
|
(a64_clz $I32 (orr_imm $I32 (rbit $I32 x) (u64_into_imm_logic $I32 0x800000))))
|
|
|
|
(rule (lower (has_type $I16 (ctz x)))
|
|
(a64_clz $I32 (orr_imm $I32 (rbit $I32 x) (u64_into_imm_logic $I32 0x8000))))
|
|
|
|
(rule (lower (has_type $I128 (ctz x)))
|
|
(let ((val ValueRegs x)
|
|
(lo Reg (rbit $I64 (value_regs_get val 0)))
|
|
(hi Reg (rbit $I64 (value_regs_get val 1))))
|
|
(lower_clz128 (value_regs hi lo))))
|
|
|
|
(rule (lower (has_type ty (ctz x)))
|
|
(a64_clz ty (rbit ty x)))
|
|
|
|
;;;; Rules for `cls` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
(rule (lower (has_type $I8 (cls x)))
|
|
(sub_imm $I32 (a64_cls $I32 (put_in_reg_zext32 x)) (u8_into_imm12 24)))
|
|
|
|
(rule (lower (has_type $I16 (cls x)))
|
|
(sub_imm $I32 (a64_cls $I32 (put_in_reg_zext32 x)) (u8_into_imm12 16)))
|
|
|
|
;; cls lo_cls, lo
|
|
;; cls hi_cls, hi
|
|
;; eon sign_eq_eor, hi, lo
|
|
;; lsr sign_eq, sign_eq_eor, #63
|
|
;; madd lo_sign_bits, out_lo, sign_eq, sign_eq
|
|
;; cmp hi_cls, #63
|
|
;; csel maybe_lo, lo_sign_bits, xzr, eq
|
|
;; add out_lo, maybe_lo, hi_cls
|
|
;; mov out_hi, 0
|
|
(rule (lower (has_type $I128 (cls x)))
|
|
(let ((val ValueRegs x)
|
|
(lo Reg (value_regs_get val 0))
|
|
(hi Reg (value_regs_get val 1))
|
|
(lo_cls Reg (a64_cls $I64 lo))
|
|
(hi_cls Reg (a64_cls $I64 hi))
|
|
(sign_eq_eon Reg (eon $I64 hi lo))
|
|
(sign_eq Reg (lsr_imm $I64 sign_eq_eon (imm_shift_from_u8 63)))
|
|
(lo_sign_bits Reg (madd64 lo_cls sign_eq sign_eq))
|
|
(maybe_lo Reg (with_flags_reg
|
|
(cmp64_imm hi_cls (u8_into_imm12 63))
|
|
(csel (Cond.Eq) lo_sign_bits (zero_reg)))))
|
|
(value_regs (add $I64 maybe_lo hi_cls) (imm $I64 0))))
|
|
|
|
(rule (lower (has_type ty (cls x)))
|
|
(a64_cls ty x))
|
|
|
|
;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
;; The implementation of `popcnt` for scalar types is done by moving the value
|
|
;; into a vector register, using the `cnt` instruction, and then collating the
|
|
;; result back into a normal register.
|
|
;;
|
|
;; The general sequence emitted here is
|
|
;;
|
|
;; fmov tmp, in_lo
|
|
;; if ty == i128:
|
|
;; mov tmp.d[1], in_hi
|
|
;;
|
|
;; cnt tmp.16b, tmp.16b / cnt tmp.8b, tmp.8b
|
|
;; addv tmp, tmp.16b / addv tmp, tmp.8b / addp tmp.8b, tmp.8b, tmp.8b / (no instruction for 8-bit inputs)
|
|
;;
|
|
;; umov out_lo, tmp.b[0]
|
|
;; if ty == i128:
|
|
;; mov out_hi, 0
|
|
|
|
(rule (lower (has_type $I8 (popcnt x)))
|
|
(let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
|
|
(nbits Reg (vec_cnt tmp (VectorSize.Size8x8))))
|
|
(mov_from_vec nbits 0 (VectorSize.Size8x16))))
|
|
|
|
;; Note that this uses `addp` instead of `addv` as it's usually cheaper.
|
|
(rule (lower (has_type $I16 (popcnt x)))
|
|
(let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
|
|
(nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
|
|
(added Reg (addp nbits nbits (VectorSize.Size8x8))))
|
|
(mov_from_vec added 0 (VectorSize.Size8x16))))
|
|
|
|
(rule (lower (has_type $I32 (popcnt x)))
|
|
(let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
|
|
(nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
|
|
(added Reg (addv nbits (VectorSize.Size8x8))))
|
|
(mov_from_vec added 0 (VectorSize.Size8x16))))
|
|
|
|
(rule (lower (has_type $I64 (popcnt x)))
|
|
(let ((tmp Reg (mov_to_fpu x (ScalarSize.Size64)))
|
|
(nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
|
|
(added Reg (addv nbits (VectorSize.Size8x8))))
|
|
(mov_from_vec added 0 (VectorSize.Size8x16))))
|
|
|
|
(rule (lower (has_type $I128 (popcnt x)))
|
|
(let ((val ValueRegs x)
|
|
(tmp_half Reg (mov_to_fpu (value_regs_get val 0) (ScalarSize.Size64)))
|
|
(tmp Reg (mov_to_vec tmp_half (value_regs_get val 1) 1 (VectorSize.Size64x2)))
|
|
(nbits Reg (vec_cnt tmp (VectorSize.Size8x16)))
|
|
(added Reg (addv nbits (VectorSize.Size8x16))))
|
|
(value_regs (mov_from_vec added 0 (VectorSize.Size8x16)) (imm $I64 0))))
|
|
|
|
(rule (lower (has_type $I8X16 (popcnt x)))
|
|
(vec_cnt x (VectorSize.Size8x16)))
|