a1b39276e1
The tests for the SIMD floating-point maximum and minimum operations require particular care because the handling of the NaN values is non-deterministic and may vary between platforms. There is no way to match several NaN values in a test, so the solution is to extract the non-deterministic test cases into a separate file that is subsequently replicated for every backend under test, with adjustments made to the expected results. Copyright (c) 2021, Arm Limited.
297 lines
6.1 KiB
Plaintext
297 lines
6.1 KiB
Plaintext
test simple_preopt
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target aarch64
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target x86_64
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;; 64-bits platforms.
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function %iadd_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = iadd v0, v1
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return v2
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}
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; sameln: function %iadd_imm
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; nextln: block0(v0: i32):
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; nextln: v1 = iconst.i32 2
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; nextln: v2 = iadd_imm v0, 2
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; nextln: return v2
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; nextln: }
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function %isub_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = isub v0, v1
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return v2
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}
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; sameln: function %isub_imm
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; nextln: block0(v0: i32):
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; nextln: v1 = iconst.i32 2
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; nextln: v2 = iadd_imm v0, -2
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; nextln: return v2
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; nextln: }
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function %icmp_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = icmp slt v0, v1
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v3 = bint.i32 v2
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return v3
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}
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; sameln: function %icmp_imm
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; nextln: block0(v0: i32):
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; nextln: v1 = iconst.i32 2
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; nextln: v2 = icmp_imm slt v0, 2
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; nextln: v3 = bint.i32 v2
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; nextln: return v3
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; nextln: }
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function %brz_bint(i32) {
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block0(v0: i32):
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v3 = icmp_imm slt v0, 0
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v1 = bint.i32 v3
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v2 = select v1, v1, v1
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trapz v1, user0
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brz v1, block1
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jump block2
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block1:
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return
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block2:
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return
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}
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; sameln: function %brz_bint
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; nextln: (v0: i32):
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; nextln: v3 = icmp_imm slt v0, 0
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; nextln: v1 = bint.i32 v3
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; nextln: v2 = select v3, v1, v1
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; nextln: trapz v3, user0
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; nextln: brnz v3, block2
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; nextln: jump block1
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function %irsub_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = isub v1, v0
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return v2
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}
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; sameln: function %irsub_imm
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; nextln: block0(v0: i32):
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; nextln: v1 = iconst.i32 2
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; nextln: v2 = irsub_imm v0, 2
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; nextln: return v2
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; nextln: }
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;; Sign-extensions.
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;; 8 -> 16
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function %uextend_8_16() -> i16 {
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block0:
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v0 = iconst.i16 37
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v1 = ishl_imm v0, 8
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v2 = ushr_imm v1, 8
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return v2
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}
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; sameln: function %uextend_8_16
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; nextln: block0:
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; nextln: v0 = iconst.i16 37
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; nextln: v1 = ishl_imm v0, 8
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; nextln: v3 = ireduce.i8 v0
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; nextln: v2 = uextend.i16 v3
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; nextln: return v2
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; nextln: }
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function %sextend_8_16() -> i16 {
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block0:
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v0 = iconst.i16 37
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v1 = ishl_imm v0, 8
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v2 = sshr_imm v1, 8
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return v2
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}
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; sameln: function %sextend_8_16
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; nextln: block0:
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; nextln: v0 = iconst.i16 37
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; nextln: v1 = ishl_imm v0, 8
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; nextln: v3 = ireduce.i8 v0
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; nextln: v2 = sextend.i16 v3
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; nextln: return v2
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; nextln: }
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;; 8 -> 32
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function %uextend_8_32() -> i32 {
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block0:
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v0 = iconst.i32 37
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v1 = ishl_imm v0, 24
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v2 = ushr_imm v1, 24
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return v2
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}
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; sameln: function %uextend_8_32
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; nextln: block0:
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; nextln: v0 = iconst.i32 37
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; nextln: v1 = ishl_imm v0, 24
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; nextln: v3 = ireduce.i8 v0
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; nextln: v2 = uextend.i32 v3
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; nextln: return v2
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; nextln: }
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function %sextend_8_32() -> i32 {
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block0:
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v0 = iconst.i32 37
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v1 = ishl_imm v0, 24
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v2 = sshr_imm v1, 24
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return v2
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}
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; sameln: function %sextend_8_32
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; nextln: block0:
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; nextln: v0 = iconst.i32 37
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; nextln: v1 = ishl_imm v0, 24
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; nextln: v3 = ireduce.i8 v0
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; nextln: v2 = sextend.i32 v3
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; nextln: return v2
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; nextln: }
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;; 16 -> 32
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function %uextend_16_32() -> i32 {
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block0:
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v0 = iconst.i32 37
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v1 = ishl_imm v0, 16
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v2 = ushr_imm v1, 16
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return v2
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}
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; sameln: function %uextend_16_32
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; nextln: block0:
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; nextln: v0 = iconst.i32 37
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; nextln: v1 = ishl_imm v0, 16
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; nextln: v3 = ireduce.i16 v0
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; nextln: v2 = uextend.i32 v3
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; nextln: return v2
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; nextln: }
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function %sextend_16_32() -> i32 {
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block0:
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v0 = iconst.i32 37
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v1 = ishl_imm v0, 16
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v2 = sshr_imm v1, 16
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return v2
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}
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; sameln: function %sextend_16_32
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; nextln: block0:
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; nextln: v0 = iconst.i32 37
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; nextln: v1 = ishl_imm v0, 16
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; nextln: v3 = ireduce.i16 v0
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; nextln: v2 = sextend.i32 v3
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; nextln: return v2
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; nextln: }
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;; 8 -> 64
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function %uextend_8_64() -> i64 {
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block0:
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v0 = iconst.i64 37
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v1 = ishl_imm v0, 56
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v2 = ushr_imm v1, 56
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return v2
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}
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; sameln: function %uextend_8_64
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; nextln: block0:
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; nextln: v0 = iconst.i64 37
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; nextln: v1 = ishl_imm v0, 56
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; nextln: v3 = ireduce.i8 v0
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; nextln: v2 = uextend.i64 v3
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; nextln: return v2
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; nextln: }
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function %sextend_8_64() -> i64 {
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block0:
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v0 = iconst.i64 37
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v1 = ishl_imm v0, 56
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v2 = sshr_imm v1, 56
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return v2
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}
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; sameln: function %sextend_8_64
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; nextln: block0:
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; nextln: v0 = iconst.i64 37
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; nextln: v1 = ishl_imm v0, 56
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; nextln: v3 = ireduce.i8 v0
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; nextln: v2 = sextend.i64 v3
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; nextln: return v2
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; nextln: }
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;; 16 -> 64
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function %uextend_16_64() -> i64 {
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block0:
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v0 = iconst.i64 37
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v1 = ishl_imm v0, 48
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v2 = ushr_imm v1, 48
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return v2
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}
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; sameln: function %uextend_16_64
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; nextln: block0:
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; nextln: v0 = iconst.i64 37
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; nextln: v1 = ishl_imm v0, 48
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; nextln: v3 = ireduce.i16 v0
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; nextln: v2 = uextend.i64 v3
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; nextln: return v2
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; nextln: }
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function %sextend_16_64() -> i64 {
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block0:
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v0 = iconst.i64 37
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v1 = ishl_imm v0, 48
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v2 = sshr_imm v1, 48
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return v2
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}
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; sameln: function %sextend_16_64
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; nextln: block0:
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; nextln: v0 = iconst.i64 37
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; nextln: v1 = ishl_imm v0, 48
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; nextln: v3 = ireduce.i16 v0
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; nextln: v2 = sextend.i64 v3
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; nextln: return v2
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; nextln: }
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;; 32 -> 64
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function %uextend_32_64() -> i64 {
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block0:
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v0 = iconst.i64 37
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v1 = ishl_imm v0, 32
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v2 = ushr_imm v1, 32
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return v2
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}
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; sameln: function %uextend_32_64
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; nextln: block0:
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; nextln: v0 = iconst.i64 37
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; nextln: v1 = ishl_imm v0, 32
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; nextln: v3 = ireduce.i32 v0
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; nextln: v2 = uextend.i64 v3
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; nextln: return v2
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; nextln: }
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function %sextend_32_64() -> i64 {
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block0:
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v0 = iconst.i64 37
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v1 = ishl_imm v0, 32
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v2 = sshr_imm v1, 32
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return v2
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}
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; sameln: function %sextend_32_64
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; nextln: block0:
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; nextln: v0 = iconst.i64 37
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; nextln: v1 = ishl_imm v0, 32
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; nextln: v3 = ireduce.i32 v0
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; nextln: v2 = sextend.i64 v3
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; nextln: return v2
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; nextln: }
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function %add_imm_fold(i32) -> i32 {
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block0(v0: i32):
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v1 = iadd_imm v0, 42
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v2 = iadd_imm v1, -42
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return v2
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}
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; sameln: function %add_imm_fold(i32)
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; nextln: block0(v0: i32):
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; nextln: v2 -> v0
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; nextln: v1 = iadd_imm v0, 42
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; nextln: nop
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; nextln: return v2
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