T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Files
e64fb6ab39e75cf7bd573e20651365787a9f5bb2
wasmtime/tests/misc_testsuite/relaxed-simd/relaxed_laneselect.wast
Alex Crichton 8bb183f16e Implement the relaxed SIMD proposal (#5892) 
* Initial support for the Relaxed SIMD proposal

This commit adds initial scaffolding and support for the Relaxed SIMD
proposal for WebAssembly. Codegen support is supported on the x64 and
AArch64 backends on this time.

The purpose of this commit is to get all the boilerplate out of the way
in terms of plumbing through a new feature, adding tests, etc. The tests
are copied from the upstream repository at this time while the
WebAssembly/testsuite repository hasn't been updated.

A summary of changes made in this commit are:

* Lowerings for all relaxed simd opcodes have been added, currently all
  exhibiting deterministic behavior. This means that few lowerings are
  optimal on the x86 backend, but on the AArch64 backend, for example,
  all lowerings should be optimal.

* Support is added to codegen to, eventually, conditionally generate
  different code based on input codegen flags. This is intended to
  enable codegen to more efficient instructions on x86 by default, for
  example, while still allowing embedders to force
  architecture-independent semantics and behavior. One good example of
  this is the `f32x4.relaxed_fmadd` instruction which when deterministic
  forces the `fma` instruction, but otherwise if the backend doesn't
  have support for `fma` then intermediate operations are performed
  instead.

* Lowerings of `iadd_pairwise` for `i16x8` and `i32x4` were added to the
  x86 backend as they're now exercised by the deterministic lowerings of
  relaxed simd instructions.

* Sample codegen tests for added for x86 and aarch64 for some relaxed
  simd instructions.

* Wasmtime embedder support for the relaxed-simd proposal and forcing
  determinism have been added to `Config` and the CLI.

* Support has been added to the `*.wast` runtime execution for the
  `(either ...)` matcher used in the relaxed-simd proposal.

* Tests for relaxed-simd are run both with a default `Engine` as well as
  a "force deterministic" `Engine` to test both configurations.

* All tests from the upstream repository were copied into Wasmtime.
  These tests should be deleted when WebAssembly/testsuite is updated.

* x64: Add x86-specific lowerings for relaxed simd

This commit builds on the prior commit and adds an array of `x86_*`
instructions to Cranelift which have semantics that match their
corresponding x86 equivalents. Translation for relaxed simd is then
additionally updated to conditionally generate different CLIF for
relaxed simd instructions depending on whether the target is x86 or not.
This means that for AArch64 no changes are made but for x86 most relaxed
instructions now lower to some x86-equivalent with slightly different
semantics than the "deterministic" lowering.

* Add libcall support for fma to Wasmtime

This will be required to implement the `f32x4.relaxed_madd` instruction
(and others) when an x86 host doesn't specify the `has_fma` feature.

* Ignore relaxed-simd tests on s390x and riscv64

* Enable relaxed-simd tests on s390x

* Update cranelift/codegen/meta/src/shared/instructions.rs

Co-authored-by: Andrew Brown <andrew.brown@intel.com>

* Add a FIXME from review

* Add notes about deterministic semantics

* Don't default `has_native_fma` to `true`

* Review comments and rebase fixes

---------

Co-authored-by: Andrew Brown <andrew.brown@intel.com>
2023-03-07 15:52:41 +00:00

93 lines
5.7 KiB
Plaintext
Raw Blame History

;; Tests for i8x16.relaxed_laneselect, i16x8.relaxed_laneselect, i32x4.relaxed_laneselect, and i64x2.relaxed_laneselect.
(module
(func (export "i8x16.relaxed_laneselect") (param v128 v128 v128) (result v128) (i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)))
(func (export "i16x8.relaxed_laneselect") (param v128 v128 v128) (result v128) (i16x8.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)))
(func (export "i32x4.relaxed_laneselect") (param v128 v128 v128) (result v128) (i32x4.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)))
(func (export "i64x2.relaxed_laneselect") (param v128 v128 v128) (result v128) (i64x2.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2)))
(func (export "i8x16.relaxed_laneselect_cmp") (param v128 v128 v128) (result v128)
(i8x16.eq
(i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))
(i8x16.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))))
(func (export "i16x8.relaxed_laneselect_cmp") (param v128 v128 v128) (result v128)
(i16x8.eq
(i16x8.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))
(i16x8.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))))
(func (export "i32x4.relaxed_laneselect_cmp") (param v128 v128 v128) (result v128)
(i32x4.eq
(i32x4.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))
(i32x4.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))))
(func (export "i64x2.relaxed_laneselect_cmp") (param v128 v128 v128) (result v128)
(i64x2.eq
(i64x2.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))
(i64x2.relaxed_laneselect (local.get 0) (local.get 1) (local.get 2))))
)
(assert_return (invoke "i8x16.relaxed_laneselect"
(v128.const i8x16 0 1 0x12 0x12 4 5 6 7 8 9 10 11 12 13 14 15)
(v128.const i8x16 16 17 0x34 0x34 20 21 22 23 24 25 26 27 28 29 30 31)
(v128.const i8x16 0xff 0 0xf0 0x0f 0 0 0 0 0 0 0 0 0 0 0 0))
(either (v128.const i8x16 0 17 0x14 0x32 20 21 22 23 24 25 26 27 28 29 30 31)
(v128.const i8x16 0 17 0x12 0x34 20 21 22 23 24 25 26 27 28 29 30 31)))
(assert_return (invoke "i16x8.relaxed_laneselect"
(v128.const i16x8 0 1 0x1234 0x1234 4 5 6 7)
(v128.const i16x8 8 9 0x5678 0x5678 12 13 14 15)
(v128.const i16x8 0xffff 0 0xff00 0x00ff 0 0 0 0))
(either (v128.const i16x8 0 9 0x1278 0x5634 12 13 14 15)
(v128.const i16x8 0 9 0x1234 0x5678 12 13 14 15)))
(assert_return (invoke "i32x4.relaxed_laneselect"
(v128.const i32x4 0 1 0x12341234 0x12341234)
(v128.const i32x4 4 5 0x56785678 0x56785678)
(v128.const i32x4 0xffffffff 0 0xffff0000 0x0000ffff))
(either (v128.const i32x4 0 5 0x12345678 0x56781234)
(v128.const i32x4 0 5 0x12341234 0x56785678)))
(assert_return (invoke "i64x2.relaxed_laneselect"
(v128.const i64x2 0 1)
(v128.const i64x2 2 3)
(v128.const i64x2 0xffffffffffffffff 0))
(either (v128.const i64x2 0 3)
(v128.const i64x2 0 3)))
(assert_return (invoke "i64x2.relaxed_laneselect"
(v128.const i64x2 0x1234123412341234 0x1234123412341234)
(v128.const i64x2 0x5678567856785678 0x5678567856785678)
(v128.const i64x2 0xffffffff00000000 0x00000000ffffffff))
(either (v128.const i64x2 0x1234123456785678 0x5678567812341234)
(v128.const i64x2 0x1234123412341234 0x5678567856785678)))
;; Check that multiple calls to the relaxed instruction with same inputs returns same results.
(assert_return (invoke "i8x16.relaxed_laneselect_cmp"
(v128.const i8x16 0 1 0x12 0x12 4 5 6 7 8 9 10 11 12 13 14 15)
(v128.const i8x16 16 17 0x34 0x34 20 21 22 23 24 25 26 27 28 29 30 31)
(v128.const i8x16 0xff 0 0xf0 0x0f 0 0 0 0 0 0 0 0 0 0 0 0))
(v128.const i8x16 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1))
(assert_return (invoke "i16x8.relaxed_laneselect_cmp"
(v128.const i16x8 0 1 0x1234 0x1234 4 5 6 7)
(v128.const i16x8 8 9 0x5678 0x5678 12 13 14 15)
(v128.const i16x8 0xffff 0 0xff00 0x00ff 0 0 0 0))
(v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1))
(assert_return (invoke "i32x4.relaxed_laneselect_cmp"
(v128.const i32x4 0 1 0x12341234 0x12341234)
(v128.const i32x4 4 5 0x56785678 0x56785678)
(v128.const i32x4 0xffffffff 0 0xffff0000 0x0000ffff))
(v128.const i32x4 -1 -1 -1 -1))
(assert_return (invoke "i64x2.relaxed_laneselect_cmp"
(v128.const i64x2 0 1)
(v128.const i64x2 2 3)
(v128.const i64x2 0xffffffffffffffff 0))
(v128.const i64x2 -1 -1))
(assert_return (invoke "i64x2.relaxed_laneselect_cmp"
(v128.const i64x2 0x1234123412341234 0x1234123412341234)
(v128.const i64x2 0x5678567856785678 0x5678567856785678)
(v128.const i64x2 0xffffffff00000000 0x00000000ffffffff))
(v128.const i64x2 -1 -1))
Reference in New Issue View Git Blame Copy Permalink