8bb183f16e
* Initial support for the Relaxed SIMD proposal This commit adds initial scaffolding and support for the Relaxed SIMD proposal for WebAssembly. Codegen support is supported on the x64 and AArch64 backends on this time. The purpose of this commit is to get all the boilerplate out of the way in terms of plumbing through a new feature, adding tests, etc. The tests are copied from the upstream repository at this time while the WebAssembly/testsuite repository hasn't been updated. A summary of changes made in this commit are: * Lowerings for all relaxed simd opcodes have been added, currently all exhibiting deterministic behavior. This means that few lowerings are optimal on the x86 backend, but on the AArch64 backend, for example, all lowerings should be optimal. * Support is added to codegen to, eventually, conditionally generate different code based on input codegen flags. This is intended to enable codegen to more efficient instructions on x86 by default, for example, while still allowing embedders to force architecture-independent semantics and behavior. One good example of this is the `f32x4.relaxed_fmadd` instruction which when deterministic forces the `fma` instruction, but otherwise if the backend doesn't have support for `fma` then intermediate operations are performed instead. * Lowerings of `iadd_pairwise` for `i16x8` and `i32x4` were added to the x86 backend as they're now exercised by the deterministic lowerings of relaxed simd instructions. * Sample codegen tests for added for x86 and aarch64 for some relaxed simd instructions. * Wasmtime embedder support for the relaxed-simd proposal and forcing determinism have been added to `Config` and the CLI. * Support has been added to the `*.wast` runtime execution for the `(either ...)` matcher used in the relaxed-simd proposal. * Tests for relaxed-simd are run both with a default `Engine` as well as a "force deterministic" `Engine` to test both configurations. * All tests from the upstream repository were copied into Wasmtime. These tests should be deleted when WebAssembly/testsuite is updated. * x64: Add x86-specific lowerings for relaxed simd This commit builds on the prior commit and adds an array of `x86_*` instructions to Cranelift which have semantics that match their corresponding x86 equivalents. Translation for relaxed simd is then additionally updated to conditionally generate different CLIF for relaxed simd instructions depending on whether the target is x86 or not. This means that for AArch64 no changes are made but for x86 most relaxed instructions now lower to some x86-equivalent with slightly different semantics than the "deterministic" lowering. * Add libcall support for fma to Wasmtime This will be required to implement the `f32x4.relaxed_madd` instruction (and others) when an x86 host doesn't specify the `has_fma` feature. * Ignore relaxed-simd tests on s390x and riscv64 * Enable relaxed-simd tests on s390x * Update cranelift/codegen/meta/src/shared/instructions.rs Co-authored-by: Andrew Brown <andrew.brown@intel.com> * Add a FIXME from review * Add notes about deterministic semantics * Don't default `has_native_fma` to `true` * Review comments and rebase fixes --------- Co-authored-by: Andrew Brown <andrew.brown@intel.com>
107 lines
5.8 KiB
Plaintext
107 lines
5.8 KiB
Plaintext
;; Tests for relaxed dot products.
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(module
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(func (export "i16x8.relaxed_dot_i8x16_i7x16_s") (param v128 v128) (result v128) (i16x8.relaxed_dot_i8x16_i7x16_s (local.get 0) (local.get 1)))
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(func (export "i32x4.relaxed_dot_i8x16_i7x16_add_s") (param v128 v128 v128) (result v128) (i32x4.relaxed_dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2)))
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(func (export "i16x8.relaxed_dot_i8x16_i7x16_s_cmp") (param v128 v128) (result v128)
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(i16x8.eq
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(i16x8.relaxed_dot_i8x16_i7x16_s (local.get 0) (local.get 1))
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(i16x8.relaxed_dot_i8x16_i7x16_s (local.get 0) (local.get 1))))
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(func (export "i32x4.relaxed_dot_i8x16_i7x16_add_s_cmp") (param v128 v128 v128) (result v128)
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(i16x8.eq
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(i32x4.relaxed_dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2))
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(i32x4.relaxed_dot_i8x16_i7x16_add_s (local.get 0) (local.get 1) (local.get 2))))
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)
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;; Simple values to ensure things are functional.
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(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s"
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(v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)
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(v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15))
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(v128.const i16x8 1 13 41 85 145 221 313 421))
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;; Test max and min i8 values;
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(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s"
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(v128.const i8x16 -128 -128 127 127 0 0 0 0 0 0 0 0 0 0 0 0)
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(v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0))
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(v128.const i16x8 -32512 32258 0 0 0 0 0 0))
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;; signed * unsigned : -128 * 129 * 2 = -33,024 saturated to -32,768
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;; signed * signed : -128 * -127 * 2 = 32,512
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;; unsigned * unsigned : 128 * 129 * 2 = 33,024
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(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s"
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(v128.const i8x16 -128 -128 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
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(v128.const i8x16 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0 0 0))
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(either
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(v128.const i16x8 -32768 0 0 0 0 0 0 0)
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(v128.const i16x8 32512 0 0 0 0 0 0 0)
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(v128.const i16x8 33024 0 0 0 0 0 0 0)))
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;; Simple values to ensure things are functional.
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(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s"
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(v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)
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(v128.const i8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)
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(v128.const i32x4 0 1 2 3))
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;; intermediate result is [14, 126, 366, 734]
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(v128.const i32x4 14 127 368 737))
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;; Test max and min i8 values;
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(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s"
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(v128.const i8x16 -128 -128 -128 -128 127 127 127 127 0 0 0 0 0 0 0 0)
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(v128.const i8x16 127 127 127 127 127 127 127 127 0 0 0 0 0 0 0 0)
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(v128.const i32x4 1 2 3 4))
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;; intermediate result is [-65024, 64516, 0, 0]
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(v128.const i32x4 -65023 64518 3 4))
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;; signed * unsigned : -128 * 129 * 4 = -66,048 (+ 1) VPDPBUSD AVX2-VNNI or AVX512-VNNI
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;; signed * unsigned with intermediate saturation :
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;; (-128 * 129) + (-128 * 129) = -33024 saturated to -32768 (PMADDUBSW)
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;; -32768 + -32768 = -65536 (+ 1)
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;; signed * signed : -128 * -127 * 4 = 65,024 (+ 1)
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;; unsigned * unsigned : 128 * 129 * 2 = 66,048 (+ 1)
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(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s"
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(v128.const i8x16 -128 -128 -128 -128 0 0 0 0 0 0 0 0 0 0 0 0)
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(v128.const i8x16 -127 -127 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0)
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(v128.const i32x4 1 2 3 4))
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(either
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(v128.const i32x4 -66047 2 3 4)
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(v128.const i32x4 -65535 2 3 4)
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(v128.const i32x4 65025 2 3 4)
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(v128.const i32x4 66049 2 3 4)))
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;; Check that multiple calls to the relaxed instruction with same inputs returns same results.
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;; Test max and min i8 values;
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(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s_cmp"
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(v128.const i8x16 -128 -128 127 127 0 0 0 0 0 0 0 0 0 0 0 0)
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(v128.const i8x16 127 127 127 127 0 0 0 0 0 0 0 0 0 0 0 0))
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(v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1))
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;; Test max and min i8 values;
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(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s_cmp"
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(v128.const i8x16 -128 -128 -128 -128 127 127 127 127 0 0 0 0 0 0 0 0)
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(v128.const i8x16 127 127 127 127 127 127 127 127 0 0 0 0 0 0 0 0)
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(v128.const i32x4 1 2 3 4))
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;; intermediate result is [-65024, 64516, 0, 0]
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(v128.const i32x4 -1 -1 -1 -1))
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;; signed * unsigned : -128 * 129 * 2 = -33,024 saturated to -32,768
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;; signed * signed : -128 * -127 * 2 = 32,512
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;; unsigned * unsigned : 128 * 129 * 2 = 33,024
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(assert_return (invoke "i16x8.relaxed_dot_i8x16_i7x16_s_cmp"
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(v128.const i8x16 -128 -128 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
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(v128.const i8x16 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0 0 0))
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(v128.const i16x8 -1 -1 -1 -1 -1 -1 -1 -1))
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;; signed * unsigned : -128 * 129 * 4 = -66,048 (+ 1) VPDPBUSD AVX2-VNNI or AVX512-VNNI
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;; signed * unsigned with intermediate saturation :
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;; (-128 * 129) + (-128 * 129) = -33024 saturated to -32768 (PMADDUBSW)
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;; -32768 + -32768 = -65536 (+ 1)
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;; signed * signed : -128 * -127 * 4 = 65,024 (+ 1)
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;; unsigned * unsigned : 128 * 129 * 2 = 66,048 (+ 1)
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(assert_return (invoke "i32x4.relaxed_dot_i8x16_i7x16_add_s_cmp"
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(v128.const i8x16 -128 -128 -128 -128 0 0 0 0 0 0 0 0 0 0 0 0)
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(v128.const i8x16 -127 -127 -127 -127 0 0 0 0 0 0 0 0 0 0 0 0)
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(v128.const i32x4 1 2 3 4))
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(v128.const i32x4 -1 -1 -1 -1))
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