2d5db92a9e
Our previous implementation of unwind infrastructure was somewhat complex and brittle: it parsed generated instructions in order to reverse-engineer unwind info from prologues. It also relied on some fragile linkage to communicate instruction-layout information that VCode was not designed to provide. A much simpler, more reliable, and easier-to-reason-about approach is to embed unwind directives as pseudo-instructions in the prologue as we generate it. That way, we can say what we mean and just emit it directly. The usual reasoning that leads to the reverse-engineering approach is that metadata is hard to keep in sync across optimization passes; but here, (i) prologues are generated at the very end of the pipeline, and (ii) if we ever do a post-prologue-gen optimization, we can treat unwind directives as black boxes with unknown side-effects, just as we do for some other pseudo-instructions today. It turns out that it was easier to just build this for both x64 and aarch64 (since they share a factored-out ABI implementation), and wire up the platform-specific unwind-info generation for Windows and SystemV. Now we have simpler unwind on all platforms and we can delete the old unwind infra as soon as we remove the old backend. There were a few consequences to supporting Fastcall unwind in particular that led to a refactor of the common ABI. Windows only supports naming clobbered-register save locations within 240 bytes of the frame-pointer register, whatever one chooses that to be (RSP or RBP). We had previously saved clobbers below the fixed frame (and below nominal-SP). The 240-byte range has to include the old RBP too, so we're forced to place clobbers at the top of the frame, just below saved RBP/RIP. This is fine; we always keep a frame pointer anyway because we use it to refer to stack args. It does mean that offsets of fixed-frame slots (spillslots, stackslots) from RBP are no longer known before we do regalloc, so if we ever want to index these off of RBP rather than nominal-SP because we add support for `alloca` (dynamic frame growth), then we'll need a "nominal-BP" mode that is resolved after regalloc and clobber-save code is generated. I added a comment to this effect in `abi_impl.rs`. The above refactor touched both x64 and aarch64 because of shared code. This had a further effect in that the old aarch64 prologue generation subtracted from `sp` once to allocate space, then used stores to `[sp, offset]` to save clobbers. Unfortunately the offset only has 7-bit range, so if there are enough clobbered registers (and there can be -- aarch64 has 384 bytes of registers; at least one unit test hits this) the stores/loads will be out-of-range. I really don't want to synthesize large-offset sequences here; better to go back to the simpler pre-index/post-index `stp r1, r2, [sp, #-16]` form that works just like a "push". It's likely not much worse microarchitecturally (dependence chain on SP, but oh well) and it actually saves an instruction if there's no other frame to allocate. As a further advantage, it's much simpler to understand; simpler is usually better. This PR adds the new backend on Windows to CI as well.
279 lines
5.8 KiB
Plaintext
279 lines
5.8 KiB
Plaintext
test compile
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set unwind_info=false
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target aarch64
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function %stack_addr_small() -> i64 {
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ss0 = explicit_slot 8
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block0:
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v0 = stack_addr.i64 ss0
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return v0
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub sp, sp, #16
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; nextln: mov x0, sp
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; nextln: add sp, sp, #16
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %stack_addr_big() -> i64 {
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ss0 = explicit_slot 100000
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ss1 = explicit_slot 8
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block0:
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v0 = stack_addr.i64 ss0
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return v0
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz w16, #34480
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; nextln: movk w16, #1, LSL #16
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; nextln: sub sp, sp, x16, UXTX
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; nextln: mov x0, sp
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; nextln: movz w16, #34480
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; nextln: movk w16, #1, LSL #16
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; nextln: add sp, sp, x16, UXTX
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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; FIXME: don't use stack_addr legalization for stack_load and stack_store
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function %stack_load_small() -> i64 {
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ss0 = explicit_slot 8
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block0:
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v0 = stack_load.i64 ss0
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return v0
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub sp, sp, #16
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; nextln: mov x0, sp
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; nextln: ldr x0, [x0]
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; nextln: add sp, sp, #16
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %stack_load_big() -> i64 {
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ss0 = explicit_slot 100000
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ss1 = explicit_slot 8
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block0:
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v0 = stack_load.i64 ss0
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return v0
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz w16, #34480
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; nextln: movk w16, #1, LSL #16
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; nextln: sub sp, sp, x16, UXTX
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; nextln: mov x0, sp
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; nextln: ldr x0, [x0]
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; nextln: movz w16, #34480
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; nextln: movk w16, #1, LSL #16
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; nextln: add sp, sp, x16, UXTX
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %stack_store_small(i64) {
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ss0 = explicit_slot 8
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block0(v0: i64):
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stack_store.i64 v0, ss0
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return
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub sp, sp, #16
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; nextln: mov x1, sp
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; nextln: str x0, [x1]
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; nextln: add sp, sp, #16
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %stack_store_big(i64) {
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ss0 = explicit_slot 100000
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ss1 = explicit_slot 8
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block0(v0: i64):
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stack_store.i64 v0, ss0
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return
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz w16, #34480
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; nextln: movk w16, #1, LSL #16
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; nextln: sub sp, sp, x16, UXTX
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; nextln: mov x1, sp
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; nextln: str x0, [x1]
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; nextln: movz w16, #34480
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; nextln: movk w16, #1, LSL #16
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; nextln: add sp, sp, x16, UXTX
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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; Force a b1 to be spilled into a slot at an SP offset between 0x100 and
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; 0x1fff, to exercise the scaled addressing mode.
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function %b1_spill_slot(b1) -> b1, i64 {
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ss0 = explicit_slot 1000
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block0(v0: b1):
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v1 = iconst.i64 1
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v2 = iconst.i64 2
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v3 = iconst.i64 3
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v4 = iconst.i64 4
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v5 = iconst.i64 5
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v6 = iconst.i64 6
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v7 = iconst.i64 7
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v8 = iconst.i64 8
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v9 = iconst.i64 9
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v10 = iconst.i64 10
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v11 = iconst.i64 11
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v12 = iconst.i64 12
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v13 = iconst.i64 13
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v14 = iconst.i64 14
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v15 = iconst.i64 15
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v16 = iconst.i64 16
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v17 = iconst.i64 17
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v18 = iconst.i64 18
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v19 = iconst.i64 19
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v20 = iconst.i64 20
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v21 = iconst.i64 21
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v22 = iconst.i64 22
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v23 = iconst.i64 23
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v24 = iconst.i64 24
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v25 = iconst.i64 25
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v26 = iconst.i64 26
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v27 = iconst.i64 27
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v28 = iconst.i64 28
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v29 = iconst.i64 29
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v30 = iconst.i64 30
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v31 = iconst.i64 31
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v32 = iconst.i64 32
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v33 = iconst.i64 33
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v34 = iconst.i64 34
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v35 = iconst.i64 35
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v36 = iconst.i64 36
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v37 = iconst.i64 37
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v38 = iconst.i64 38
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v39 = iconst.i64 39
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v40 = iconst.i64 30
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v41 = iconst.i64 31
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v42 = iconst.i64 32
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v43 = iconst.i64 33
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v44 = iconst.i64 34
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v45 = iconst.i64 35
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v46 = iconst.i64 36
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v47 = iconst.i64 37
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v48 = iconst.i64 38
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v49 = iconst.i64 39
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v50 = iconst.i64 30
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v51 = iconst.i64 31
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v52 = iconst.i64 32
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v53 = iconst.i64 33
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v54 = iconst.i64 34
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v55 = iconst.i64 35
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v56 = iconst.i64 36
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v57 = iconst.i64 37
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v58 = iconst.i64 38
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v59 = iconst.i64 39
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v60 = iconst.i64 30
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v61 = iconst.i64 31
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v62 = iconst.i64 32
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v63 = iconst.i64 33
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v64 = iconst.i64 34
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v65 = iconst.i64 35
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v66 = iconst.i64 36
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v67 = iconst.i64 37
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v68 = iconst.i64 38
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v69 = iconst.i64 39
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v70 = iadd.i64 v1, v2
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v71 = iadd.i64 v3, v4
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v72 = iadd.i64 v5, v6
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v73 = iadd.i64 v7, v8
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v74 = iadd.i64 v9, v10
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v75 = iadd.i64 v11, v12
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v76 = iadd.i64 v13, v14
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v77 = iadd.i64 v15, v16
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v78 = iadd.i64 v17, v18
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v79 = iadd.i64 v19, v20
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v80 = iadd.i64 v21, v22
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v81 = iadd.i64 v23, v24
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v82 = iadd.i64 v25, v26
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v83 = iadd.i64 v27, v28
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v84 = iadd.i64 v29, v30
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v85 = iadd.i64 v31, v32
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v86 = iadd.i64 v33, v34
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v87 = iadd.i64 v35, v36
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v88 = iadd.i64 v37, v38
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v89 = iadd.i64 v39, v40
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v90 = iadd.i64 v41, v42
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v91 = iadd.i64 v43, v44
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v92 = iadd.i64 v45, v46
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v93 = iadd.i64 v47, v48
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v94 = iadd.i64 v49, v50
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v95 = iadd.i64 v51, v52
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v96 = iadd.i64 v53, v54
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v97 = iadd.i64 v55, v56
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v98 = iadd.i64 v57, v58
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v99 = iadd.i64 v59, v60
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v100 = iadd.i64 v61, v62
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v101 = iadd.i64 v63, v64
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v102 = iadd.i64 v65, v66
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v103 = iadd.i64 v67, v68
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v104 = iadd.i64 v69, v70
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v105 = iadd.i64 v71, v72
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v106 = iadd.i64 v73, v74
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v107 = iadd.i64 v75, v76
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v108 = iadd.i64 v77, v78
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v109 = iadd.i64 v79, v80
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v110 = iadd.i64 v81, v82
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v111 = iadd.i64 v83, v84
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v112 = iadd.i64 v85, v86
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v113 = iadd.i64 v87, v88
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v114 = iadd.i64 v89, v90
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v115 = iadd.i64 v91, v92
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v116 = iadd.i64 v93, v94
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v117 = iadd.i64 v95, v96
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v118 = iadd.i64 v97, v98
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v119 = iadd.i64 v99, v100
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v120 = iadd.i64 v101, v102
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v121 = iadd.i64 v103, v104
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v122 = iadd.i64 v105, v106
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v123 = iadd.i64 v107, v108
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v124 = iadd.i64 v109, v110
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v125 = iadd.i64 v111, v112
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v126 = iadd.i64 v113, v114
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v127 = iadd.i64 v115, v116
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v128 = iadd.i64 v117, v118
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v129 = iadd.i64 v119, v120
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v130 = iadd.i64 v121, v122
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v131 = iadd.i64 v123, v124
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v132 = iadd.i64 v125, v126
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v133 = iadd.i64 v127, v128
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v134 = iadd.i64 v129, v130
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v135 = iadd.i64 v131, v132
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v136 = iadd.i64 v133, v134
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v137 = iadd.i64 v135, v136
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return v0, v137
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}
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