2d5db92a9e
Our previous implementation of unwind infrastructure was somewhat complex and brittle: it parsed generated instructions in order to reverse-engineer unwind info from prologues. It also relied on some fragile linkage to communicate instruction-layout information that VCode was not designed to provide. A much simpler, more reliable, and easier-to-reason-about approach is to embed unwind directives as pseudo-instructions in the prologue as we generate it. That way, we can say what we mean and just emit it directly. The usual reasoning that leads to the reverse-engineering approach is that metadata is hard to keep in sync across optimization passes; but here, (i) prologues are generated at the very end of the pipeline, and (ii) if we ever do a post-prologue-gen optimization, we can treat unwind directives as black boxes with unknown side-effects, just as we do for some other pseudo-instructions today. It turns out that it was easier to just build this for both x64 and aarch64 (since they share a factored-out ABI implementation), and wire up the platform-specific unwind-info generation for Windows and SystemV. Now we have simpler unwind on all platforms and we can delete the old unwind infra as soon as we remove the old backend. There were a few consequences to supporting Fastcall unwind in particular that led to a refactor of the common ABI. Windows only supports naming clobbered-register save locations within 240 bytes of the frame-pointer register, whatever one chooses that to be (RSP or RBP). We had previously saved clobbers below the fixed frame (and below nominal-SP). The 240-byte range has to include the old RBP too, so we're forced to place clobbers at the top of the frame, just below saved RBP/RIP. This is fine; we always keep a frame pointer anyway because we use it to refer to stack args. It does mean that offsets of fixed-frame slots (spillslots, stackslots) from RBP are no longer known before we do regalloc, so if we ever want to index these off of RBP rather than nominal-SP because we add support for `alloca` (dynamic frame growth), then we'll need a "nominal-BP" mode that is resolved after regalloc and clobber-save code is generated. I added a comment to this effect in `abi_impl.rs`. The above refactor touched both x64 and aarch64 because of shared code. This had a further effect in that the old aarch64 prologue generation subtracted from `sp` once to allocate space, then used stores to `[sp, offset]` to save clobbers. Unfortunately the offset only has 7-bit range, so if there are enough clobbered registers (and there can be -- aarch64 has 384 bytes of registers; at least one unit test hits this) the stores/loads will be out-of-range. I really don't want to synthesize large-offset sequences here; better to go back to the simpler pre-index/post-index `stp r1, r2, [sp, #-16]` form that works just like a "push". It's likely not much worse microarchitecturally (dependence chain on SP, but oh well) and it actually saves an instruction if there's no other frame to allocate. As a further advantage, it's much simpler to understand; simpler is usually better. This PR adds the new backend on Windows to CI as well.
428 lines
8.1 KiB
Plaintext
428 lines
8.1 KiB
Plaintext
test compile
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set unwind_info=false
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target aarch64
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function %f1(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = iadd.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: add x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f2(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = isub.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f3(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = imul.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: madd x0, x0, x1, xzr
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f4(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = umulhi.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: umulh x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f5(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = smulhi.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: smulh x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f6(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sdiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: adds xzr, x1, #1
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; nextln: ccmp x0, #1, #nzcv, eq
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; nextln: b.vc 8 ; udf
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; nextln: mov x0, x2
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f7(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x2, #2
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; nextln: sdiv x1, x0, x2
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; nextln: cbnz x2, 8 ; udf
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; nextln: adds xzr, x2, #1
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; nextln: ccmp x0, #1, #nzcv, eq
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; nextln: b.vc 8 ; udf
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; nextln: mov x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f8(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = udiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f9(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = udiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x1, #2
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f10(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = srem.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sdiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: msub x0, x2, x1, x0
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f11(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = urem.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: udiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: msub x0, x2, x1, x0
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f12(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x3, w0
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; nextln: sxtw x2, w1
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; nextln: sdiv x0, x3, x2
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; nextln: cbnz x2, 8 ; udf
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; nextln: adds wzr, w2, #1
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; nextln: ccmp w3, #1, #nzcv, eq
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; nextln: b.vc 8 ; udf
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f13(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x0, w0
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; nextln: movz x1, #2
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; nextln: sxtw x2, w1
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; nextln: sdiv x1, x0, x2
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; nextln: cbnz x2, 8 ; udf
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; nextln: adds wzr, w2, #1
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; nextln: ccmp w0, #1, #nzcv, eq
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; nextln: b.vc 8 ; udf
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; nextln: mov x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f14(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = udiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: mov w1, w1
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f15(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = udiv.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: movz x1, #2
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; nextln: udiv x0, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f16(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = srem.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x0, w0
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; nextln: sxtw x1, w1
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; nextln: sdiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: msub x0, x2, x1, x0
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f17(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = urem.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: mov w1, w1
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; nextln: udiv x2, x0, x1
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; nextln: cbnz x1, 8 ; udf
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; nextln: msub x0, x2, x1, x0
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f18(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = band.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: and x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f19(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bor.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orr x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f20(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bxor.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: eor x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f21(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = band_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: bic x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f22(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bor_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orn x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f23(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bxor_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: eon x0, x0, x1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f24(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bnot.i64 v0
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orn x0, xzr, x0
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f25(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = iconst.i32 53
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v3 = ishl.i32 v0, v2
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v4 = isub.i32 v1, v3
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return v4
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub w0, w1, w0, LSL 21
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f26(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 -1
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v2 = iadd.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub w0, w0, #1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f27(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 -1
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v2 = isub.i32 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: add w0, w0, #1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f28(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 -1
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v2 = isub.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: add x0, x0, #1
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f29(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 1
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v2 = ineg v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x0, #1
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; nextln: sub x0, xzr, x0
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f30(i8x16) -> i8x16 {
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block0(v0: i8x16):
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v1 = iconst.i64 1
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v2 = ushr.i8x16 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x0, #1
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; nextln: sub w0, wzr, w0
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; nextln: dup v1.16b, w0
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; nextln: ushl v0.16b, v0.16b, v1.16b
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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