a0318f36f0
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
152 lines
3.1 KiB
Plaintext
152 lines
3.1 KiB
Plaintext
test compile precise-output
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target x86_64
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function u0:0(i64 sarg(64)) -> i8 system_v {
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block0(v0: i64):
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v1 = load.i8 v0
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return v1
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; lea 16(%rbp), %rsi
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; movzbq 0(%rsi), %rax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function u0:1(i64 sarg(64), i64) -> i8 system_v {
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block0(v0: i64, v1: i64):
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v2 = load.i8 v1
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v3 = load.i8 v0
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v4 = iadd.i8 v2, v3
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return v4
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; lea 16(%rbp), %rsi
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; movzbq 0(%rdi), %rax
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; movzbq 0(%rsi), %r11
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; addl %eax, %r11d, %eax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function u0:2(i64) -> i8 system_v {
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fn1 = colocated u0:0(i64 sarg(64)) -> i8 system_v
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block0(v0: i64):
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v1 = call fn1(v0)
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return v1
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rdi, %r8
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; subq %rsp, $64, %rsp
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; virtual_sp_offset_adjust 64
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; lea 0(%rsp), %rdi
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; movq %r8, %rsi
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; movl $64, %edx
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; load_ext_name %Memcpy+0, %rcx
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; call *%rcx
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; call User { namespace: 0, index: 0 }
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; addq %rsp, $64, %rsp
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; virtual_sp_offset_adjust -64
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function u0:3(i64, i64) -> i8 system_v {
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fn1 = colocated u0:0(i64, i64 sarg(64)) -> i8 system_v
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block0(v0: i64, v1: i64):
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v2 = call fn1(v0, v1)
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return v2
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; subq %rsp, $16, %rsp
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; movq %r12, 0(%rsp)
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; block0:
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; movq %rdi, %r12
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; subq %rsp, $64, %rsp
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; virtual_sp_offset_adjust 64
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; lea 0(%rsp), %rdi
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; movl $64, %edx
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; load_ext_name %Memcpy+0, %rcx
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; call *%rcx
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; movq %r12, %rdi
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; call User { namespace: 0, index: 0 }
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; addq %rsp, $64, %rsp
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; virtual_sp_offset_adjust -64
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; movq 0(%rsp), %r12
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; addq %rsp, $16, %rsp
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function u0:4(i64 sarg(128), i64 sarg(64)) -> i8 system_v {
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block0(v0: i64, v1: i64):
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v2 = load.i8 v0
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v3 = load.i8 v1
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v4 = iadd.i8 v2, v3
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return v4
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; lea 16(%rbp), %rsi
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; lea 144(%rbp), %rdi
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; movzbq 0(%rsi), %rax
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; movzbq 0(%rdi), %r11
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; addl %eax, %r11d, %eax
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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function u0:5(i64, i64, i64) -> i8 system_v {
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fn1 = colocated u0:0(i64, i64 sarg(128), i64 sarg(64)) -> i8 system_v
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block0(v0: i64, v1: i64, v2: i64):
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v3 = call fn1(v0, v1, v2)
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return v3
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}
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; pushq %rbp
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; movq %rsp, %rbp
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; subq %rsp, $16, %rsp
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; movq %rbx, 0(%rsp)
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; movq %r14, 8(%rsp)
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; block0:
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; movq %rdi, %r14
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; movq %rdx, %rbx
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; subq %rsp, $192, %rsp
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; virtual_sp_offset_adjust 192
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; lea 0(%rsp), %rdi
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; movl $128, %edx
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; load_ext_name %Memcpy+0, %rcx
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; call *%rcx
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; lea 128(%rsp), %rdi
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; movq %rbx, %rsi
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; movl $64, %edx
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; load_ext_name %Memcpy+0, %rcx
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; call *%rcx
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; movq %r14, %rdi
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; call User { namespace: 0, index: 0 }
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; addq %rsp, $192, %rsp
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; virtual_sp_offset_adjust -192
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; movq 0(%rsp), %rbx
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; movq 8(%rsp), %r14
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; addq %rsp, $16, %rsp
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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