teapotd e430984ac4 Improve bitselect codegen with knowledge of operand origin (#1783) ...

* Encode vselect using BLEND instructions on x86

* Legalize vselect to bitselect

* Optimize bitselect to vselect for some operands

* Add run tests for bitselect-vselect optimization

* Address review feedback

2020-05-29 19:53:11 -07:00

..

cdsl

Add DerivedFunction for splitting lane widths and doubling the number of lanes

2020-04-23 10:55:54 -07:00

isa

Improve bitselect codegen with knowledge of operand origin (#1783)

2020-05-29 19:53:11 -07:00

shared

Fix typo in sadd_sat instruction definition

2020-05-26 09:55:26 +02:00

default_map.rs

Add documentation for top-level items in cranelift-codegen/meta

2019-10-31 09:35:08 -07:00

error.rs

Add documentation for top-level items in cranelift-codegen/meta

2019-10-31 09:35:08 -07:00

gen_binemit.rs

Fix clippy warnings.

2019-10-24 17:20:12 -07:00

gen_encodings.rs

Fix clippy warnings.

2019-10-24 17:20:12 -07:00

gen_inst.rs

cranelift: Sign extend Imm64 immediates

2020-05-12 15:44:48 -07:00

gen_legalizer.rs

Avoid unused import warnings in generated legalizer code (#1393)

2020-02-20 09:58:19 -08:00

gen_registers.rs

Remove dependency on hard-coded ordering of x86 register banks

2020-03-06 10:53:22 -08:00

gen_settings.rs

Add documentation for top-level items in cranelift-codegen/meta

2019-10-31 09:35:08 -07:00

gen_types.rs

[meta] Make more things pub(crate) instead of pub;

2019-09-23 14:42:20 +02:00

lib.rs

Add documentation for top-level items in cranelift-codegen/meta

2019-10-31 09:35:08 -07:00

srcgen.rs

[meta] Add more pub(crate) definitions.

2019-10-29 14:23:10 +01:00

unique_table.rs

Add documentation for top-level items in cranelift-codegen/meta

2019-10-31 09:35:08 -07:00