Andrew Brown f1904bffea Add x86 SIMD sshr and ushr ...

Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.

2019-10-15 15:51:50 -07:00

..

filetests

Add x86 SIMD sshr and ushr

2019-10-15 15:51:50 -07:00

src

Reorganise optimisation level settings, and make the insn shrink pass optional (#1044)

2019-09-19 18:51:25 +02:00

Cargo.toml

Bump version to 0.46.1

2019-10-15 11:11:48 -07:00

LICENSE

moved crates in lib/ to src/, renamed crates, modified some files' text (#660)

2019-01-28 15:56:54 -08:00