dd7fa81b20
This commit goes through the `runtests` folder of the `filetests` test suite and ensure that everything which uses simd or float-related instructions on x64 is executed with the baseline support for x86_64 in addition to adding in AVX support. Most of the instructions used have AVX equivalents so this should help test all of the equivalents in addition to the codegen filetests in the x64 folder.
45 lines
1.4 KiB
Plaintext
45 lines
1.4 KiB
Plaintext
test run
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target aarch64
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target s390x
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set enable_simd
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target x86_64 has_sse3 has_ssse3 has_sse41
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target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
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function %scalartovector_i32(i32) -> i32x4 {
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block0(v0: i32):
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v1 = scalar_to_vector.i32x4 v0
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return v1
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}
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; run: %scalartovector_i32(1) == [1 0 0 0]
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; run: %scalartovector_i32(4294967295) == [4294967295 0 0 0]
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function %scalartovector_i64(i64) -> i64x2 {
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block0(v0: i64):
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v1 = scalar_to_vector.i64x2 v0
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return v1
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}
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; run: %scalartovector_i64(1) == [1 0]
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; run: %scalartovector_i64(18446744073709551615) == [18446744073709551615 0]
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function %scalartovector_f32(f32) -> f32x4 {
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block0(v0: f32):
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v1 = scalar_to_vector.f32x4 v0
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return v1
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}
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; run: %scalartovector_f32(0x1.0) == [0x1.0 0x0.0 0x0.0 0x0.0]
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; run: %scalartovector_f32(0x0.1) == [0x0.1 0x0.0 0x0.0 0x0.0]
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; run: %scalartovector_f32(NaN) == [NaN 0x0.0 0x0.0 0x0.0]
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; run: %scalartovector_f32(-0x0.0) == [-0x0.0 0x0.0 0x0.0 0x0.0]
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; run: %scalartovector_f32(0x0.0) == [0x0.0 0x0.0 0x0.0 0x0.0]
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function %scalartovector_f64(f64) -> f64x2 {
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block0(v0: f64):
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v1 = scalar_to_vector.f64x2 v0
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return v1
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}
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; run: %scalartovector_f64(0x1.0) == [0x1.0 0x0.0]
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; run: %scalartovector_f64(0x0.1) == [0x0.1 0x0.0]
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; run: %scalartovector_f64(NaN) == [NaN 0x0.0]
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; run: %scalartovector_f64(-0x0.0) == [-0x0.0 0x0.0]
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; run: %scalartovector_f64(0x0.0) == [0x0.0 0x0.0]
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