Jakob Stoklund Olesen dcad3fa339 Fix coloring bug with combined constraints and global values. ...

The Intel instruction "v1 = ushr v2, v2" will implicitly fix the output
register for v2 to %rcx because the output is tied to the first input
operand and the second input operand is fixed to %rcx.

Make sure we handle this transitive constraint when checking for
interference with the globally live registers.

Fixes #218

2018-01-17 15:51:08 -08:00

..

meta

Illegalize rbp/r13 for zero-offset loads on Intel x64 (#225)

2018-01-16 20:05:53 -08:00

src

Fix coloring bug with combined constraints and global values.

2018-01-17 15:51:08 -08:00

build.rs

Update rustfmt to 0.9.0.

2017-08-31 10:44:59 -07:00

Cargo.toml

Move library crates under 'lib/'.

2016-10-17 14:44:43 -07:00