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dc874a5b3bc506dc5b91a99c6096af7f01dabeb5
wasmtime/cranelift/codegen/src/isa/x86
History
Andrew Brown dc874a5b3b Infer REX prefixes for SIMD load_extend
2020-04-02 11:28:42 -07:00
..
abi.rs
Mass rename Ebb and relatives to Block (#1365)
2020-02-07 10:46:47 -06:00
binemit.rs
Infer REX prefix for SIMD operations; fixes #1127
2020-03-18 10:12:50 -07:00
enc_tables.rs
Infer REX prefixes for SIMD load_extend
2020-04-02 11:28:42 -07:00
fde.rs
Remove duplication of map_reg; fixes #1245
2020-03-31 15:42:02 -07:00
mod.rs
Remove duplication of map_reg; fixes #1245
2020-03-31 15:42:02 -07:00
registers.rs
Remove FPR32; fixes #1303
2020-03-17 12:46:41 -07:00
settings.rs
[meta] Remove mentions to Python in comments of the non-meta crate;
2019-07-05 17:50:17 +02:00
unwind.rs
Remove dependency on hard-coded ordering of x86 register banks
2020-03-06 10:53:22 -08:00
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