d9e6902b69
* Support full set of ADD LOGICAL / SUBTRACT LOGICAL instructions * Full implementation of IaddIfcout lowering * Enable most memory64 tests (except simd and threads)
806 lines
27 KiB
Rust
806 lines
27 KiB
Rust
//! Implementation of a standard S390x ABI.
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//!
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//! This machine uses the "vanilla" ABI implementation from abi_impl.rs,
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//! however a few details are different from the description there:
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//!
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//! - On s390x, the caller must provide a "register save area" of 160
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//! bytes to any function it calls. The called function is free to use
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//! this space for any purpose; usually to save callee-saved GPRs.
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//! (Note that while this area is allocated by the caller, it is counted
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//! as part of the callee's stack frame; in particular, the callee's CFA
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//! is the top of the register save area, not the incoming SP value.)
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//!
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//! - Overflow arguments are passed on the stack starting immediately
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//! above the register save area. On s390x, this space is allocated
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//! only once directly in the prologue, using a size large enough to
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//! hold overflow arguments for every call in the function.
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//!
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//! - On s390x we do not use a frame pointer register; instead, every
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//! element of the stack frame is addressed via (constant) offsets
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//! from the stack pointer. Note that due to the above (and because
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//! there are no variable-sized stack allocations in cranelift), the
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//! value of the stack pointer register never changes after the
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//! initial allocation in the function prologue.
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//!
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//! Overall, the stack frame layout on s390x is as follows:
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//!
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//! ```plain
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//! (high address)
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//!
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//! +---------------------------+
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//! | ... |
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//! CFA -----> | stack args |
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//! +---------------------------+
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//! | ... |
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//! | 160 bytes reg save area |
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//! SP at function entry -----> | (used to save GPRs) |
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//! +---------------------------+
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//! | ... |
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//! | clobbered callee-saves |
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//! | (used to save FPRs) |
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//! unwind-frame base ----> | (alloc'd by prologue) |
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//! +---------------------------+
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//! | ... |
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//! | spill slots |
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//! | (accessed via nominal SP) |
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//! | ... |
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//! | stack slots |
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//! | (accessed via nominal SP) |
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//! nominal SP ---------------> | (alloc'd by prologue) |
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//! +---------------------------+
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//! | ... |
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//! | args for call |
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//! | outgoing reg save area |
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//! SP during function ------> | (alloc'd by prologue) |
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//! +---------------------------+
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//!
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//! (low address)
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//! ```
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use crate::ir;
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use crate::ir::condcodes::IntCC;
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use crate::ir::types;
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use crate::ir::MemFlags;
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use crate::ir::Type;
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use crate::isa;
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use crate::isa::s390x::inst::*;
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use crate::isa::unwind::UnwindInst;
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use crate::machinst::*;
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use crate::settings;
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use crate::{CodegenError, CodegenResult};
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use regalloc::{RealReg, Reg, RegClass, Set, Writable};
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use smallvec::{smallvec, SmallVec};
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use std::convert::TryFrom;
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// We use a generic implementation that factors out ABI commonalities.
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/// Support for the S390x ABI from the callee side (within a function body).
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pub type S390xABICallee = ABICalleeImpl<S390xMachineDeps>;
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/// Support for the S390x ABI from the caller side (at a callsite).
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pub type S390xABICaller = ABICallerImpl<S390xMachineDeps>;
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/// ABI Register usage
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fn in_int_reg(ty: Type) -> bool {
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match ty {
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types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => true,
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types::B1 | types::B8 | types::B16 | types::B32 | types::B64 => true,
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_ => false,
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}
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}
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fn in_flt_reg(ty: Type) -> bool {
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match ty {
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types::F32 | types::F64 => true,
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_ => false,
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}
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}
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fn get_intreg_for_arg(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::gpr(2)),
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1 => Some(regs::gpr(3)),
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2 => Some(regs::gpr(4)),
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3 => Some(regs::gpr(5)),
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4 => Some(regs::gpr(6)),
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_ => None,
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}
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}
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fn get_fltreg_for_arg(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::fpr(0)),
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1 => Some(regs::fpr(2)),
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2 => Some(regs::fpr(4)),
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3 => Some(regs::fpr(6)),
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_ => None,
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}
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}
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fn get_intreg_for_ret(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::gpr(2)),
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// ABI extension to support multi-value returns:
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1 => Some(regs::gpr(3)),
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2 => Some(regs::gpr(4)),
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3 => Some(regs::gpr(5)),
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_ => None,
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}
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}
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fn get_fltreg_for_ret(idx: usize) -> Option<Reg> {
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match idx {
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0 => Some(regs::fpr(0)),
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// ABI extension to support multi-value returns:
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1 => Some(regs::fpr(2)),
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2 => Some(regs::fpr(4)),
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3 => Some(regs::fpr(6)),
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_ => None,
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}
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}
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/// This is the limit for the size of argument and return-value areas on the
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/// stack. We place a reasonable limit here to avoid integer overflow issues
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/// with 32-bit arithmetic: for now, 128 MB.
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static STACK_ARG_RET_SIZE_LIMIT: u64 = 128 * 1024 * 1024;
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impl Into<MemArg> for StackAMode {
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fn into(self) -> MemArg {
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match self {
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StackAMode::FPOffset(off, _ty) => MemArg::InitialSPOffset { off },
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StackAMode::NominalSPOffset(off, _ty) => MemArg::NominalSPOffset { off },
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StackAMode::SPOffset(off, _ty) => {
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MemArg::reg_plus_off(stack_reg(), off, MemFlags::trusted())
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}
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}
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}
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}
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/// S390x-specific ABI behavior. This struct just serves as an implementation
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/// point for the trait; it is never actually instantiated.
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pub struct S390xMachineDeps;
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impl ABIMachineSpec for S390xMachineDeps {
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type I = Inst;
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fn word_bits() -> u32 {
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64
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}
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/// Return required stack alignment in bytes.
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fn stack_align(_call_conv: isa::CallConv) -> u32 {
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8
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}
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fn compute_arg_locs(
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call_conv: isa::CallConv,
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_flags: &settings::Flags,
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params: &[ir::AbiParam],
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args_or_rets: ArgsOrRets,
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add_ret_area_ptr: bool,
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) -> CodegenResult<(Vec<ABIArg>, i64, Option<usize>)> {
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let mut next_gpr = 0;
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let mut next_fpr = 0;
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let mut next_stack: u64 = 0;
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let mut ret = vec![];
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if args_or_rets == ArgsOrRets::Args {
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next_stack = 160;
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}
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for i in 0..params.len() {
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let param = ¶ms[i];
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// Validate "purpose".
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match ¶m.purpose {
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&ir::ArgumentPurpose::VMContext
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| &ir::ArgumentPurpose::Normal
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| &ir::ArgumentPurpose::StackLimit
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| &ir::ArgumentPurpose::SignatureId => {}
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_ => panic!(
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"Unsupported argument purpose {:?} in signature: {:?}",
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param.purpose, params
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),
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}
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let intreg = in_int_reg(param.value_type);
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let fltreg = in_flt_reg(param.value_type);
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debug_assert!(intreg || fltreg);
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debug_assert!(!(intreg && fltreg));
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let (next_reg, candidate) = if intreg {
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let candidate = match args_or_rets {
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ArgsOrRets::Args => get_intreg_for_arg(next_gpr),
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ArgsOrRets::Rets => get_intreg_for_ret(next_gpr),
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};
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(&mut next_gpr, candidate)
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} else {
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let candidate = match args_or_rets {
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ArgsOrRets::Args => get_fltreg_for_arg(next_fpr),
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ArgsOrRets::Rets => get_fltreg_for_ret(next_fpr),
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};
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(&mut next_fpr, candidate)
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};
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// In the Wasmtime ABI only the first return value can be in a register.
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let candidate =
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if call_conv.extends_wasmtime() && args_or_rets == ArgsOrRets::Rets && i > 0 {
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None
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} else {
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candidate
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};
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if let Some(reg) = candidate {
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ret.push(ABIArg::reg(
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reg.to_real_reg(),
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param.value_type,
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param.extension,
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param.purpose,
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));
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*next_reg += 1;
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} else {
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// Compute size. Every argument or return value takes a slot of
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// at least 8 bytes, except for return values in the Wasmtime ABI.
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let size = (ty_bits(param.value_type) / 8) as u64;
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let slot_size = if call_conv.extends_wasmtime() && args_or_rets == ArgsOrRets::Rets
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{
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size
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} else {
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std::cmp::max(size, 8)
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};
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// Align the stack slot.
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debug_assert!(slot_size.is_power_of_two());
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next_stack = align_to(next_stack, slot_size);
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// If the type is actually of smaller size (and the argument
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// was not extended), it is passed right-aligned.
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let offset = if size < slot_size && param.extension == ir::ArgumentExtension::None {
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slot_size - size
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} else {
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0
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};
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ret.push(ABIArg::stack(
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(next_stack + offset) as i64,
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param.value_type,
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param.extension,
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param.purpose,
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));
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next_stack += slot_size;
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}
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}
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next_stack = align_to(next_stack, 8);
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let extra_arg = if add_ret_area_ptr {
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debug_assert!(args_or_rets == ArgsOrRets::Args);
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if let Some(reg) = get_intreg_for_arg(next_gpr) {
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ret.push(ABIArg::reg(
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reg.to_real_reg(),
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types::I64,
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ir::ArgumentExtension::None,
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ir::ArgumentPurpose::Normal,
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));
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} else {
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ret.push(ABIArg::stack(
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next_stack as i64,
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types::I64,
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ir::ArgumentExtension::None,
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ir::ArgumentPurpose::Normal,
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));
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next_stack += 8;
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}
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Some(ret.len() - 1)
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} else {
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None
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};
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// To avoid overflow issues, limit the arg/return size to something
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// reasonable -- here, 128 MB.
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if next_stack > STACK_ARG_RET_SIZE_LIMIT {
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return Err(CodegenError::ImplLimitExceeded);
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}
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Ok((ret, next_stack as i64, extra_arg))
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}
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fn fp_to_arg_offset(_call_conv: isa::CallConv, _flags: &settings::Flags) -> i64 {
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0
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}
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fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Inst {
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Inst::gen_load(into_reg, mem.into(), ty)
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}
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fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Inst {
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Inst::gen_store(mem.into(), from_reg, ty)
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}
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fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
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Inst::gen_move(to_reg, from_reg, ty)
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}
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fn gen_extend(
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to_reg: Writable<Reg>,
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from_reg: Reg,
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signed: bool,
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from_bits: u8,
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to_bits: u8,
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) -> Inst {
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assert!(from_bits < to_bits);
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Inst::Extend {
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rd: to_reg,
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rn: from_reg,
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signed,
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from_bits,
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to_bits,
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}
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}
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fn gen_ret() -> Inst {
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Inst::Ret { link: gpr(14) }
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}
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fn gen_add_imm(into_reg: Writable<Reg>, from_reg: Reg, imm: u32) -> SmallInstVec<Inst> {
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let mut insts = SmallVec::new();
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if let Some(imm) = UImm12::maybe_from_u64(imm as u64) {
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insts.push(Inst::LoadAddr {
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rd: into_reg,
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mem: MemArg::BXD12 {
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base: from_reg,
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index: zero_reg(),
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disp: imm,
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flags: MemFlags::trusted(),
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},
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});
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} else if let Some(imm) = SImm20::maybe_from_i64(imm as i64) {
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insts.push(Inst::LoadAddr {
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rd: into_reg,
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mem: MemArg::BXD20 {
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base: from_reg,
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index: zero_reg(),
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disp: imm,
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flags: MemFlags::trusted(),
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},
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});
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} else {
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if from_reg != into_reg.to_reg() {
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insts.push(Inst::mov64(into_reg, from_reg));
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}
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insts.push(Inst::AluRUImm32 {
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alu_op: ALUOp::AddLogical64,
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rd: into_reg,
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imm,
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});
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}
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insts
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}
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fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Inst> {
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let mut insts = SmallVec::new();
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insts.push(Inst::CmpTrapRR {
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op: CmpOp::CmpL64,
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rn: stack_reg(),
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rm: limit_reg,
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cond: Cond::from_intcc(IntCC::UnsignedLessThanOrEqual),
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trap_code: ir::TrapCode::StackOverflow,
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});
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insts
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}
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fn gen_epilogue_placeholder() -> Inst {
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Inst::EpiloguePlaceholder
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}
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fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>, _ty: Type) -> Inst {
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let mem = mem.into();
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Inst::LoadAddr { rd: into_reg, mem }
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}
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fn get_stacklimit_reg() -> Reg {
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spilltmp_reg()
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}
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fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Inst {
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let mem = MemArg::reg_plus_off(base, offset.into(), MemFlags::trusted());
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Inst::gen_load(into_reg, mem, ty)
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}
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fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Inst {
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let mem = MemArg::reg_plus_off(base, offset.into(), MemFlags::trusted());
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Inst::gen_store(mem, from_reg, ty)
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}
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fn gen_sp_reg_adjust(imm: i32) -> SmallInstVec<Inst> {
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if imm == 0 {
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return SmallVec::new();
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}
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let mut insts = SmallVec::new();
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if let Ok(imm) = i16::try_from(imm) {
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insts.push(Inst::AluRSImm16 {
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alu_op: ALUOp::Add64,
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rd: writable_stack_reg(),
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imm,
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});
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} else {
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insts.push(Inst::AluRSImm32 {
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alu_op: ALUOp::Add64,
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rd: writable_stack_reg(),
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imm,
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});
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}
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insts
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}
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fn gen_nominal_sp_adj(offset: i32) -> Inst {
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Inst::VirtualSPOffsetAdj {
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offset: offset.into(),
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}
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}
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fn gen_prologue_frame_setup(_flags: &settings::Flags) -> SmallInstVec<Inst> {
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SmallVec::new()
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}
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fn gen_epilogue_frame_restore(_flags: &settings::Flags) -> SmallInstVec<Inst> {
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SmallVec::new()
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}
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fn gen_probestack(_: u32) -> SmallInstVec<Self::I> {
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// TODO: implement if we ever require stack probes on an s390x host
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// (unlikely unless Lucet is ported)
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smallvec![]
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}
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// Returns stack bytes used as well as instructions. Does not adjust
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// nominal SP offset; abi_impl generic code will do that.
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fn gen_clobber_save(
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_call_conv: isa::CallConv,
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_setup_frame: bool,
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flags: &settings::Flags,
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clobbered_callee_saves: &Vec<Writable<RealReg>>,
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fixed_frame_storage_size: u32,
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outgoing_args_size: u32,
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) -> (u64, SmallVec<[Inst; 16]>) {
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let mut insts = SmallVec::new();
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let mut clobbered_fpr = vec![];
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let mut clobbered_gpr = vec![];
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for ® in clobbered_callee_saves.iter() {
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match reg.to_reg().get_class() {
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RegClass::I64 => clobbered_gpr.push(reg),
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RegClass::F64 => clobbered_fpr.push(reg),
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class => panic!("Unexpected RegClass: {:?}", class),
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}
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}
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let mut first_clobbered_gpr = 16;
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for reg in clobbered_gpr {
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let enc = reg.to_reg().get_hw_encoding();
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if enc < first_clobbered_gpr {
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first_clobbered_gpr = enc;
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}
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}
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let clobber_size = clobbered_fpr.len() * 8;
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if flags.unwind_info() {
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insts.push(Inst::Unwind {
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inst: UnwindInst::DefineNewFrame {
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offset_upward_to_caller_sp: 160,
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offset_downward_to_clobbers: clobber_size as u32,
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},
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});
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}
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// Use STMG to save clobbered GPRs into save area.
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if first_clobbered_gpr < 16 {
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let offset = 8 * first_clobbered_gpr as i64;
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insts.push(Inst::StoreMultiple64 {
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rt: gpr(first_clobbered_gpr as u8),
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rt2: gpr(15),
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addr_reg: stack_reg(),
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addr_off: SImm20::maybe_from_i64(offset).unwrap(),
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});
|
|
}
|
|
if flags.unwind_info() {
|
|
for i in first_clobbered_gpr..16 {
|
|
insts.push(Inst::Unwind {
|
|
inst: UnwindInst::SaveReg {
|
|
clobber_offset: clobber_size as u32 + (i * 8) as u32,
|
|
reg: gpr(i as u8).to_real_reg(),
|
|
},
|
|
});
|
|
}
|
|
}
|
|
|
|
// Decrement stack pointer.
|
|
let stack_size =
|
|
outgoing_args_size as i32 + clobber_size as i32 + fixed_frame_storage_size as i32;
|
|
insts.extend(Self::gen_sp_reg_adjust(-stack_size));
|
|
if flags.unwind_info() {
|
|
insts.push(Inst::Unwind {
|
|
inst: UnwindInst::StackAlloc {
|
|
size: stack_size as u32,
|
|
},
|
|
});
|
|
}
|
|
|
|
let sp_adj = outgoing_args_size as i32;
|
|
if sp_adj > 0 {
|
|
insts.push(Self::gen_nominal_sp_adj(sp_adj));
|
|
}
|
|
|
|
// Save FPRs.
|
|
for (i, reg) in clobbered_fpr.iter().enumerate() {
|
|
insts.push(Inst::FpuStore64 {
|
|
rd: reg.to_reg().to_reg(),
|
|
mem: MemArg::reg_plus_off(
|
|
stack_reg(),
|
|
(i * 8) as i64 + outgoing_args_size as i64 + fixed_frame_storage_size as i64,
|
|
MemFlags::trusted(),
|
|
),
|
|
});
|
|
if flags.unwind_info() {
|
|
insts.push(Inst::Unwind {
|
|
inst: UnwindInst::SaveReg {
|
|
clobber_offset: (i * 8) as u32,
|
|
reg: reg.to_reg(),
|
|
},
|
|
});
|
|
}
|
|
}
|
|
|
|
(clobber_size as u64, insts)
|
|
}
|
|
|
|
fn gen_clobber_restore(
|
|
call_conv: isa::CallConv,
|
|
_: &settings::Flags,
|
|
clobbers: &Set<Writable<RealReg>>,
|
|
fixed_frame_storage_size: u32,
|
|
outgoing_args_size: u32,
|
|
) -> SmallVec<[Inst; 16]> {
|
|
let mut insts = SmallVec::new();
|
|
|
|
// Collect clobbered registers.
|
|
let (clobbered_gpr, clobbered_fpr) = get_regs_saved_in_prologue(call_conv, clobbers);
|
|
let mut first_clobbered_gpr = 16;
|
|
for reg in clobbered_gpr {
|
|
let enc = reg.to_reg().get_hw_encoding();
|
|
if enc < first_clobbered_gpr {
|
|
first_clobbered_gpr = enc;
|
|
}
|
|
}
|
|
let clobber_size = clobbered_fpr.len() * 8;
|
|
|
|
// Restore FPRs.
|
|
for (i, reg) in clobbered_fpr.iter().enumerate() {
|
|
insts.push(Inst::FpuLoad64 {
|
|
rd: Writable::from_reg(reg.to_reg().to_reg()),
|
|
mem: MemArg::reg_plus_off(
|
|
stack_reg(),
|
|
(i * 8) as i64 + outgoing_args_size as i64 + fixed_frame_storage_size as i64,
|
|
MemFlags::trusted(),
|
|
),
|
|
});
|
|
}
|
|
|
|
// Increment stack pointer unless it will be restored implicitly.
|
|
let stack_size =
|
|
outgoing_args_size as i32 + clobber_size as i32 + fixed_frame_storage_size as i32;
|
|
let implicit_sp_restore = first_clobbered_gpr < 16
|
|
&& SImm20::maybe_from_i64(8 * first_clobbered_gpr as i64 + stack_size as i64).is_some();
|
|
if !implicit_sp_restore {
|
|
insts.extend(Self::gen_sp_reg_adjust(stack_size));
|
|
}
|
|
|
|
// Use LMG to restore clobbered GPRs from save area.
|
|
if first_clobbered_gpr < 16 {
|
|
let mut offset = 8 * first_clobbered_gpr as i64;
|
|
if implicit_sp_restore {
|
|
offset += stack_size as i64;
|
|
}
|
|
insts.push(Inst::LoadMultiple64 {
|
|
rt: writable_gpr(first_clobbered_gpr as u8),
|
|
rt2: writable_gpr(15),
|
|
addr_reg: stack_reg(),
|
|
addr_off: SImm20::maybe_from_i64(offset).unwrap(),
|
|
});
|
|
}
|
|
|
|
insts
|
|
}
|
|
|
|
fn gen_call(
|
|
dest: &CallDest,
|
|
uses: Vec<Reg>,
|
|
defs: Vec<Writable<Reg>>,
|
|
opcode: ir::Opcode,
|
|
tmp: Writable<Reg>,
|
|
_callee_conv: isa::CallConv,
|
|
_caller_conv: isa::CallConv,
|
|
) -> SmallVec<[(InstIsSafepoint, Inst); 2]> {
|
|
let mut insts = SmallVec::new();
|
|
match &dest {
|
|
&CallDest::ExtName(ref name, RelocDistance::Near) => insts.push((
|
|
InstIsSafepoint::Yes,
|
|
Inst::Call {
|
|
link: writable_gpr(14),
|
|
info: Box::new(CallInfo {
|
|
dest: name.clone(),
|
|
uses,
|
|
defs,
|
|
opcode,
|
|
}),
|
|
},
|
|
)),
|
|
&CallDest::ExtName(ref name, RelocDistance::Far) => {
|
|
insts.push((
|
|
InstIsSafepoint::No,
|
|
Inst::LoadExtNameFar {
|
|
rd: tmp,
|
|
name: Box::new(name.clone()),
|
|
offset: 0,
|
|
},
|
|
));
|
|
insts.push((
|
|
InstIsSafepoint::Yes,
|
|
Inst::CallInd {
|
|
link: writable_gpr(14),
|
|
info: Box::new(CallIndInfo {
|
|
rn: tmp.to_reg(),
|
|
uses,
|
|
defs,
|
|
opcode,
|
|
}),
|
|
},
|
|
));
|
|
}
|
|
&CallDest::Reg(reg) => insts.push((
|
|
InstIsSafepoint::Yes,
|
|
Inst::CallInd {
|
|
link: writable_gpr(14),
|
|
info: Box::new(CallIndInfo {
|
|
rn: *reg,
|
|
uses,
|
|
defs,
|
|
opcode,
|
|
}),
|
|
},
|
|
)),
|
|
}
|
|
|
|
insts
|
|
}
|
|
|
|
fn gen_memcpy(
|
|
_call_conv: isa::CallConv,
|
|
_dst: Reg,
|
|
_src: Reg,
|
|
_size: usize,
|
|
) -> SmallVec<[Self::I; 8]> {
|
|
unimplemented!("StructArgs not implemented for S390X yet");
|
|
}
|
|
|
|
fn get_number_of_spillslots_for_value(rc: RegClass, ty: Type) -> u32 {
|
|
// We allocate in terms of 8-byte slots.
|
|
match (rc, ty) {
|
|
(RegClass::I64, _) => 1,
|
|
(RegClass::F64, _) => 1,
|
|
_ => panic!("Unexpected register class!"),
|
|
}
|
|
}
|
|
|
|
/// Get the current virtual-SP offset from an instruction-emission state.
|
|
fn get_virtual_sp_offset_from_state(s: &EmitState) -> i64 {
|
|
s.virtual_sp_offset
|
|
}
|
|
|
|
/// Get the nominal-SP-to-FP offset from an instruction-emission state.
|
|
fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
|
|
s.initial_sp_offset
|
|
}
|
|
|
|
fn get_regs_clobbered_by_call(call_conv_of_callee: isa::CallConv) -> Vec<Writable<Reg>> {
|
|
let mut caller_saved = Vec::new();
|
|
for i in 0..15 {
|
|
let x = writable_gpr(i);
|
|
if is_reg_clobbered_by_call(call_conv_of_callee, x.to_reg().to_real_reg()) {
|
|
caller_saved.push(x);
|
|
}
|
|
}
|
|
for i in 0..15 {
|
|
let v = writable_fpr(i);
|
|
if is_reg_clobbered_by_call(call_conv_of_callee, v.to_reg().to_real_reg()) {
|
|
caller_saved.push(v);
|
|
}
|
|
}
|
|
caller_saved
|
|
}
|
|
|
|
fn get_ext_mode(
|
|
_call_conv: isa::CallConv,
|
|
specified: ir::ArgumentExtension,
|
|
) -> ir::ArgumentExtension {
|
|
specified
|
|
}
|
|
|
|
fn get_clobbered_callee_saves(
|
|
call_conv: isa::CallConv,
|
|
regs: &Set<Writable<RealReg>>,
|
|
) -> Vec<Writable<RealReg>> {
|
|
let mut regs: Vec<Writable<RealReg>> = regs
|
|
.iter()
|
|
.cloned()
|
|
.filter(|r| is_reg_saved_in_prologue(call_conv, r.to_reg()))
|
|
.collect();
|
|
|
|
// Sort registers for deterministic code output. We can do an unstable
|
|
// sort because the registers will be unique (there are no dups).
|
|
regs.sort_unstable_by_key(|r| r.to_reg().get_index());
|
|
regs
|
|
}
|
|
|
|
fn is_frame_setup_needed(
|
|
_is_leaf: bool,
|
|
_stack_args_size: u32,
|
|
_num_clobbered_callee_saves: usize,
|
|
_fixed_frame_storage_size: u32,
|
|
) -> bool {
|
|
// The call frame set-up is handled by gen_clobber_save().
|
|
false
|
|
}
|
|
}
|
|
|
|
fn is_reg_saved_in_prologue(_call_conv: isa::CallConv, r: RealReg) -> bool {
|
|
match r.get_class() {
|
|
RegClass::I64 => {
|
|
// r6 - r15 inclusive are callee-saves.
|
|
r.get_hw_encoding() >= 6 && r.get_hw_encoding() <= 15
|
|
}
|
|
RegClass::F64 => {
|
|
// f8 - f15 inclusive are callee-saves.
|
|
r.get_hw_encoding() >= 8 && r.get_hw_encoding() <= 15
|
|
}
|
|
_ => panic!("Unexpected RegClass"),
|
|
}
|
|
}
|
|
|
|
fn get_regs_saved_in_prologue(
|
|
call_conv: isa::CallConv,
|
|
regs: &Set<Writable<RealReg>>,
|
|
) -> (Vec<Writable<RealReg>>, Vec<Writable<RealReg>>) {
|
|
let mut int_saves = vec![];
|
|
let mut fpr_saves = vec![];
|
|
for ® in regs.iter() {
|
|
if is_reg_saved_in_prologue(call_conv, reg.to_reg()) {
|
|
match reg.to_reg().get_class() {
|
|
RegClass::I64 => int_saves.push(reg),
|
|
RegClass::F64 => fpr_saves.push(reg),
|
|
_ => panic!("Unexpected RegClass"),
|
|
}
|
|
}
|
|
}
|
|
// Sort registers for deterministic code output.
|
|
int_saves.sort_by_key(|r| r.to_reg().get_index());
|
|
fpr_saves.sort_by_key(|r| r.to_reg().get_index());
|
|
(int_saves, fpr_saves)
|
|
}
|
|
|
|
fn is_reg_clobbered_by_call(_call_conv: isa::CallConv, r: RealReg) -> bool {
|
|
match r.get_class() {
|
|
RegClass::I64 => {
|
|
// r0 - r5 inclusive are caller-saves.
|
|
r.get_hw_encoding() <= 5
|
|
}
|
|
RegClass::F64 => {
|
|
// f0 - f7 inclusive are caller-saves.
|
|
r.get_hw_encoding() <= 7
|
|
}
|
|
_ => panic!("Unexpected RegClass"),
|
|
}
|
|
}
|