32 lines
999 B
Python
32 lines
999 B
Python
"""
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RISC-V settings.
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"""
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from __future__ import absolute_import
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from cdsl.settings import SettingGroup, BoolSetting
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from cdsl.predicates import And
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import base.settings as shared
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from .defs import ISA
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ISA.settings = SettingGroup('riscv', parent=shared.group)
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supports_m = BoolSetting("CPU supports the 'M' extension (mul/div)")
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supports_a = BoolSetting("CPU supports the 'A' extension (atomics)")
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supports_f = BoolSetting("CPU supports the 'F' extension (float)")
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supports_d = BoolSetting("CPU supports the 'D' extension (double)")
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enable_m = BoolSetting(
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"Enable the use of 'M' instructions if available",
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default=True)
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enable_e = BoolSetting(
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"Enable the 'RV32E' instruction set with only 16 registers")
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use_m = And(supports_m, enable_m)
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use_a = And(supports_a, shared.enable_atomics)
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use_f = And(supports_f, shared.enable_float)
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use_d = And(supports_d, shared.enable_float)
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full_float = And(shared.enable_simd, supports_f, supports_d)
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ISA.settings.close(globals())
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