d76f7ee52e
This commit goes through the lowerings for the CLIF `splat` instruction
and improves the support for each operator. Many of these lowerings are
mirrored from v8/SpiderMonkey and there are a number of improvements:
* AVX2 `v{p,}broadcast*` instructions are added and used when available.
* Float-based splats are much simpler and always a single-instruction
* Integer-based splats don't insert into an uninit xmm value and instead
start out with a `movd` to move into an `xmm` register. This
thoeretically breaks dependencies with prior instructions since `movd`
creates a fresh new value in the destination register.
* Loads are now sunk into all of the instructions. A new extractor,
`sinkable_load_exact`, was added to sink the i8/i16 loads.
351 lines
6.4 KiB
Plaintext
351 lines
6.4 KiB
Plaintext
test compile precise-output
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set enable_simd
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target x86_64 has_sse3 has_ssse3 has_sse41
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;; shuffle
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function %shuffle_different_ssa_values() -> i8x16 {
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block0:
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v0 = vconst.i8x16 0x00
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v1 = vconst.i8x16 0x01
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v2 = shuffle v0, v1, 0x11000000000000000000000000000000 ;; pick the second lane of v1, the rest use the first lane of v0
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqu const(3), %xmm0
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; movdqu const(2), %xmm2
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; pshufb %xmm0, const(0), %xmm0
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; pshufb %xmm2, const(1), %xmm2
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; por %xmm0, %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqu 0x54(%rip), %xmm0
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; movdqu 0x3c(%rip), %xmm2
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; pshufb 0x13(%rip), %xmm0
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; pshufb 0x1a(%rip), %xmm2
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; por %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb $0x80, -0x7f7f7f80(%rax)
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; addb $0x80, -0x7f7f7f80(%rax)
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; addb $0, 0x101(%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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function %shuffle_same_ssa_value() -> i8x16 {
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block0:
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v1 = vconst.i8x16 0x01
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v2 = shuffle v1, v1, 0x13000000000000000000000000000000 ;; pick the fourth lane of v1 and the rest from the first lane of v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqu const(1), %xmm0
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; pshufb %xmm0, const(0), %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqu 0x24(%rip), %xmm0
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; pshufb 0xb(%rip), %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rbx)
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; addl %eax, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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function %swizzle() -> i8x16 {
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block0:
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v0 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v2 = swizzle v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqu const(1), %xmm0
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; movdqu const(1), %xmm1
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; paddusb %xmm1, const(0), %xmm1
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; pshufb %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqu 0x34(%rip), %xmm0
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; movdqu 0x2c(%rip), %xmm1
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; paddusb 0x14(%rip), %xmm1
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; pshufb %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; jo 0xa2
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; jo 0xa4
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; jo 0xa6
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; jo 0xa8
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; jo 0xaa
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; jo 0xac
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; jo 0xae
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; jo 0xb0
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; addb %al, (%rcx)
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; addb (%rbx), %al
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; addb $5, %al
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function %splat_i8(i8) -> i8x16 {
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block0(v0: i8):
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v1 = splat.i8x16 v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movd %edi, %xmm0
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; uninit %xmm5
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; pxor %xmm5, %xmm5, %xmm5
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; pshufb %xmm0, %xmm5, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movd %edi, %xmm0
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; pxor %xmm5, %xmm5
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; pshufb %xmm5, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %splat_i16() -> i16x8 {
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block0:
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v0 = iconst.i16 -1
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v1 = splat.i16x8 v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movl $-1, %esi
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; movd %esi, %xmm2
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; pshuflw $0, %xmm2, %xmm4
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; pshufd $0, %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movl $0xffffffff, %esi
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; movd %esi, %xmm2
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; pshuflw $0, %xmm2, %xmm4
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; pshufd $0, %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %splat_i32(i32) -> i32x4 {
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block0(v0: i32):
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v1 = splat.i32x4 v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movd %edi, %xmm2
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; pshufd $0, %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movd %edi, %xmm2
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; pshufd $0, %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %splat_f64(f64) -> f64x2 {
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block0(v0: f64):
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v1 = splat.f64x2 v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movddup %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movddup %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %load32_zero_coalesced(i64) -> i32x4 {
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block0(v0: i64):
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v1 = load.i32 v0
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v2 = scalar_to_vector.i32x4 v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movss 0(%rdi), %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movss (%rdi), %xmm0 ; trap: heap_oob
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %load32_zero_int(i32) -> i32x4 {
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block0(v0: i32):
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v1 = scalar_to_vector.i32x4 v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movd %edi, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movd %edi, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %load32_zero_float(f32) -> f32x4 {
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block0(v0: f32):
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v1 = scalar_to_vector.f32x4 v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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