02ef6a02b8
* Implement `Extractlane`, `UaddSat`, and `UsubSat` for Cranelift interpreter Implemented the `Extractlane`, `UaddSat`, and `UsubSat` opcodes for the interpreter, and added helper functions for working with SIMD vectors (`extractlanes`, `vectorizelanes`, and `binary_arith`). Copyright (c) 2021, Arm Limited * Re-use tests + constrict Vector assert - Re-use interpreter tests as runtests where supported. - Constrict Vector assertion. - Code style adjustments following feedback. Copyright (c) 2021, Arm Limited * Runtest `i32x4` vectors on AArch64; add `i64x2` tests Copyright (c) 2021, Arm Limited * Add `simd-` prefix to test filenames Copyright (c) 2021, Arm Limited * Return aliased `SmallVec` from `extractlanes` Using a `SmallVec<[i128; 4]>` allows larger-width 128-bit vectors (`i32x4`, `i64x2`, ...) to not cause heap allocations. Copyright (c) 2021, Arm Limited * Accept slice to `vectorizelanes` rather than `Vec` Copyright (c) 2021, Arm Limited
This crate provides an interpreter for Cranelift IR. It is still a work in progress, as many instructions are unimplemented and various implementation gaps exist. Use at your own risk.