d4f8eb7453
* Introduce a `TargetFrontendConfig` type. `TargetFrontendConfig` is information specific to the target which is provided to frontends to allow them to produce Cranelift IR for the target. Currently this includes the pointer size and the default calling convention. The default calling convention is now inferred from the target, rather than being a setting. cranelift-native is now just a provider of target information, rather than also being a provider of settings, which gives it a clearer role. And instead of having cranelift-frontend routines require the whole `TargetIsa`, just require the `TargetFrontendConfig`, and add a way to get the `TargetFrontendConfig` from a `Module`. Fixes #529. Fixes #555.
579 lines
21 KiB
Rust
579 lines
21 KiB
Rust
//! x86 ABI implementation.
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use super::registers::{FPR, GPR, RU};
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use abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
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use cursor::{Cursor, CursorPosition, EncCursor};
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use ir;
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use ir::immediates::Imm64;
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use ir::stackslot::{StackOffset, StackSize};
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use ir::{
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get_probestack_funcref, AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, InstBuilder,
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ValueLoc,
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};
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use isa::{CallConv, RegClass, RegUnit, TargetIsa};
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use regalloc::RegisterSet;
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use result::CodegenResult;
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use stack_layout::layout_stack;
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use std::i32;
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use target_lexicon::{PointerWidth, Triple};
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/// Argument registers for x86-64
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static ARG_GPRS: [RU; 6] = [RU::rdi, RU::rsi, RU::rdx, RU::rcx, RU::r8, RU::r9];
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/// Return value registers.
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static RET_GPRS: [RU; 3] = [RU::rax, RU::rdx, RU::rcx];
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/// Argument registers for x86-64, when using windows fastcall
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static ARG_GPRS_WIN_FASTCALL_X64: [RU; 4] = [RU::rcx, RU::rdx, RU::r8, RU::r9];
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/// Return value registers for x86-64, when using windows fastcall
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static RET_GPRS_WIN_FASTCALL_X64: [RU; 1] = [RU::rax];
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struct Args {
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pointer_bytes: u8,
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pointer_bits: u8,
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pointer_type: ir::Type,
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gpr: &'static [RU],
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gpr_used: usize,
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fpr_limit: usize,
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fpr_used: usize,
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offset: u32,
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call_conv: CallConv,
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}
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impl Args {
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fn new(bits: u8, gpr: &'static [RU], fpr_limit: usize, call_conv: CallConv) -> Self {
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let offset = if let CallConv::WindowsFastcall = call_conv {
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// [1] "The caller is responsible for allocating space for parameters to the callee,
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// and must always allocate sufficient space to store four register parameters"
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32
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} else {
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0
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};
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Self {
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pointer_bytes: bits / 8,
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pointer_bits: bits,
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pointer_type: ir::Type::int(u16::from(bits)).unwrap(),
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gpr,
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gpr_used: 0,
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fpr_limit,
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fpr_used: 0,
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offset,
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call_conv,
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}
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}
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}
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impl ArgAssigner for Args {
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fn assign(&mut self, arg: &AbiParam) -> ArgAction {
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let ty = arg.value_type;
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// Check for a legal type.
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// We don't support SIMD yet, so break all vectors down.
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if ty.is_vector() {
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return ValueConversion::VectorSplit.into();
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}
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// Large integers and booleans are broken down to fit in a register.
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if !ty.is_float() && ty.bits() > u16::from(self.pointer_bits) {
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return ValueConversion::IntSplit.into();
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}
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// Small integers are extended to the size of a pointer register.
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if ty.is_int() && ty.bits() < u16::from(self.pointer_bits) {
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match arg.extension {
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ArgumentExtension::None => {}
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ArgumentExtension::Uext => return ValueConversion::Uext(self.pointer_type).into(),
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ArgumentExtension::Sext => return ValueConversion::Sext(self.pointer_type).into(),
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}
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}
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// Handle special-purpose arguments.
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if ty.is_int() && self.call_conv == CallConv::Baldrdash {
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match arg.purpose {
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// This is SpiderMonkey's `WasmTlsReg`.
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ArgumentPurpose::VMContext => {
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return ArgumentLoc::Reg(if self.pointer_bits == 64 {
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RU::r14
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} else {
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RU::rsi
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} as RegUnit).into()
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}
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// This is SpiderMonkey's `WasmTableCallSigReg`.
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ArgumentPurpose::SignatureId => return ArgumentLoc::Reg(RU::r10 as RegUnit).into(),
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_ => {}
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}
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}
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// Try to use a GPR.
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if !ty.is_float() && self.gpr_used < self.gpr.len() {
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let reg = self.gpr[self.gpr_used] as RegUnit;
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self.gpr_used += 1;
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return ArgumentLoc::Reg(reg).into();
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}
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// Try to use an FPR.
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if ty.is_float() && self.fpr_used < self.fpr_limit {
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let reg = FPR.unit(self.fpr_used);
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self.fpr_used += 1;
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return ArgumentLoc::Reg(reg).into();
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}
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// Assign a stack location.
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let loc = ArgumentLoc::Stack(self.offset as i32);
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self.offset += u32::from(self.pointer_bytes);
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debug_assert!(self.offset <= i32::MAX as u32);
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loc.into()
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}
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}
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/// Legalize `sig`.
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pub fn legalize_signature(sig: &mut ir::Signature, triple: &Triple, _current: bool) {
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let bits;
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let mut args;
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match triple.pointer_width().unwrap() {
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PointerWidth::U16 => panic!(),
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PointerWidth::U32 => {
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bits = 32;
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args = Args::new(bits, &[], 0, sig.call_conv);
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}
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PointerWidth::U64 => {
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bits = 64;
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args = if sig.call_conv == CallConv::WindowsFastcall {
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Args::new(bits, &ARG_GPRS_WIN_FASTCALL_X64[..], 4, sig.call_conv)
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} else {
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Args::new(bits, &ARG_GPRS[..], 8, sig.call_conv)
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};
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}
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}
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legalize_args(&mut sig.params, &mut args);
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let regs = if sig.call_conv == CallConv::WindowsFastcall {
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&RET_GPRS_WIN_FASTCALL_X64[..]
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} else {
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&RET_GPRS[..]
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};
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let mut rets = Args::new(bits, regs, 2, sig.call_conv);
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legalize_args(&mut sig.returns, &mut rets);
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}
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/// Get register class for a type appearing in a legalized signature.
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pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
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if ty.is_int() || ty.is_bool() {
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GPR
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} else {
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FPR
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}
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}
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/// Get the set of allocatable registers for `func`.
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pub fn allocatable_registers(_func: &ir::Function, triple: &Triple) -> RegisterSet {
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let mut regs = RegisterSet::new();
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regs.take(GPR, RU::rsp as RegUnit);
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regs.take(GPR, RU::rbp as RegUnit);
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// 32-bit arch only has 8 registers.
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if triple.pointer_width().unwrap() != PointerWidth::U64 {
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for i in 8..16 {
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regs.take(GPR, GPR.unit(i));
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regs.take(FPR, FPR.unit(i));
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}
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}
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regs
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}
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/// Get the set of callee-saved registers.
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fn callee_saved_gprs(isa: &TargetIsa, call_conv: CallConv) -> &'static [RU] {
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match isa.triple().pointer_width().unwrap() {
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PointerWidth::U16 => panic!(),
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PointerWidth::U32 => &[RU::rbx, RU::rsi, RU::rdi],
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PointerWidth::U64 => {
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if call_conv == CallConv::WindowsFastcall {
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// "registers RBX, RBP, RDI, RSI, RSP, R12, R13, R14, R15 are considered nonvolatile
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// and must be saved and restored by a function that uses them."
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// as per https://msdn.microsoft.com/en-us/library/6t169e9c.aspx
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// RSP & RSB are not listed below, since they are restored automatically during
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// a function call. If that wasn't the case, function calls (RET) would not work.
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&[
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RU::rbx,
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RU::rdi,
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RU::rsi,
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RU::r12,
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RU::r13,
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RU::r14,
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RU::r15,
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]
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} else {
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&[RU::rbx, RU::r12, RU::r13, RU::r14, RU::r15]
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}
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}
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}
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}
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/// Get the set of callee-saved registers that are used.
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fn callee_saved_gprs_used(isa: &TargetIsa, func: &ir::Function) -> RegisterSet {
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let mut all_callee_saved = RegisterSet::empty();
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for reg in callee_saved_gprs(isa, func.signature.call_conv) {
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all_callee_saved.free(GPR, *reg as RegUnit);
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}
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let mut used = RegisterSet::empty();
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for value_loc in func.locations.values() {
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// Note that `value_loc` here contains only a single unit of a potentially multi-unit
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// register. We don't use registers that overlap each other in the x86 ISA, but in others
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// we do. So this should not be blindly reused.
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if let ValueLoc::Reg(ru) = *value_loc {
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if !used.is_avail(GPR, ru) {
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used.free(GPR, ru);
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}
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}
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}
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// regmove and regfill instructions may temporarily divert values into other registers,
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// and these are not reflected in `func.locations`. Scan the function for such instructions
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// and note which callee-saved registers they use.
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//
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// TODO: Consider re-evaluating how regmove/regfill/regspill work and whether it's possible
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// to avoid this step.
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for ebb in &func.layout {
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for inst in func.layout.ebb_insts(ebb) {
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match func.dfg[inst] {
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ir::instructions::InstructionData::RegMove { dst, .. }
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| ir::instructions::InstructionData::RegFill { dst, .. } => {
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if !used.is_avail(GPR, dst) {
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used.free(GPR, dst);
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}
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}
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_ => (),
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}
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}
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}
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used.intersect(&all_callee_saved);
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used
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}
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pub fn prologue_epilogue(func: &mut ir::Function, isa: &TargetIsa) -> CodegenResult<()> {
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match func.signature.call_conv {
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// For now, just translate fast and cold as system_v.
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CallConv::Fast | CallConv::Cold | CallConv::SystemV => {
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system_v_prologue_epilogue(func, isa)
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}
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CallConv::WindowsFastcall => fastcall_prologue_epilogue(func, isa),
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CallConv::Baldrdash => baldrdash_prologue_epilogue(func, isa),
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CallConv::Probestack => unimplemented!("probestack calling convention"),
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}
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}
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pub fn baldrdash_prologue_epilogue(func: &mut ir::Function, isa: &TargetIsa) -> CodegenResult<()> {
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debug_assert!(
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!isa.flags().probestack_enabled(),
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"baldrdash does not expect cranelift to emit stack probes"
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);
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// Baldrdash on 32-bit x86 always aligns its stack pointer to 16 bytes.
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let stack_align = 16;
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let word_size = StackSize::from(isa.pointer_bytes());
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let bytes = StackSize::from(isa.flags().baldrdash_prologue_words()) * word_size;
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let mut ss = ir::StackSlotData::new(ir::StackSlotKind::IncomingArg, bytes);
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ss.offset = Some(-(bytes as StackOffset));
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func.stack_slots.push(ss);
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layout_stack(&mut func.stack_slots, stack_align)?;
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Ok(())
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}
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/// Implementation of the fastcall-based Win64 calling convention described at [1]
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/// [1] https://msdn.microsoft.com/en-us/library/ms235286.aspx
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pub fn fastcall_prologue_epilogue(func: &mut ir::Function, isa: &TargetIsa) -> CodegenResult<()> {
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if isa.triple().pointer_width().unwrap() != PointerWidth::U64 {
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panic!("TODO: windows-fastcall: x86-32 not implemented yet");
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}
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// [1] "The primary exceptions are the stack pointer and malloc or alloca memory,
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// which are aligned to 16 bytes in order to aid performance"
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let stack_align = 16;
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let word_size = isa.pointer_bytes() as usize;
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let reg_type = isa.pointer_type();
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let csrs = callee_saved_gprs_used(isa, func);
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// [1] "Space is allocated on the call stack as a shadow store for callees to save"
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// This shadow store contains the parameters which are passed through registers (ARG_GPRS)
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// and is eventually used by the callee to save & restore the values of the arguments.
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//
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// [2] https://blogs.msdn.microsoft.com/oldnewthing/20110302-00/?p=11333
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// "Although the x64 calling convention reserves spill space for parameters,
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// you don’t have to use them as such"
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//
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// The reserved stack area is composed of:
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// return address + frame pointer + all callee-saved registers + shadow space
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//
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// Pushing the return address is an implicit function of the `call`
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// instruction. Each of the others we will then push explicitly. Then we
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// will adjust the stack pointer to make room for the rest of the required
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// space for this frame.
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const SHADOW_STORE_SIZE: i32 = 32;
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let csr_stack_size = ((csrs.iter(GPR).len() + 2) * word_size) as i32;
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// TODO: eventually use the 32 bytes (shadow store) as spill slot. This currently doesn't work
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// since cranelift does not support spill slots before incoming args
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func.create_stack_slot(ir::StackSlotData {
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kind: ir::StackSlotKind::IncomingArg,
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size: csr_stack_size as u32,
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offset: Some(-(SHADOW_STORE_SIZE + csr_stack_size)),
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});
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let total_stack_size = layout_stack(&mut func.stack_slots, stack_align)? as i32;
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let local_stack_size = i64::from(total_stack_size - csr_stack_size);
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// Add CSRs to function signature
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let fp_arg = ir::AbiParam::special_reg(
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reg_type,
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ir::ArgumentPurpose::FramePointer,
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RU::rbp as RegUnit,
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);
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func.signature.params.push(fp_arg);
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func.signature.returns.push(fp_arg);
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for csr in csrs.iter(GPR) {
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let csr_arg = ir::AbiParam::special_reg(reg_type, ir::ArgumentPurpose::CalleeSaved, csr);
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func.signature.params.push(csr_arg);
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func.signature.returns.push(csr_arg);
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}
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// Set up the cursor and insert the prologue
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let entry_ebb = func.layout.entry_block().expect("missing entry block");
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let mut pos = EncCursor::new(func, isa).at_first_insertion_point(entry_ebb);
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insert_common_prologue(&mut pos, local_stack_size, reg_type, &csrs, isa);
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|
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// Reset the cursor and insert the epilogue
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let mut pos = pos.at_position(CursorPosition::Nowhere);
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insert_common_epilogues(&mut pos, local_stack_size, reg_type, &csrs);
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|
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Ok(())
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}
|
||
|
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/// Insert a System V-compatible prologue and epilogue.
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pub fn system_v_prologue_epilogue(func: &mut ir::Function, isa: &TargetIsa) -> CodegenResult<()> {
|
||
// The original 32-bit x86 ELF ABI had a 4-byte aligned stack pointer, but
|
||
// newer versions use a 16-byte aligned stack pointer.
|
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let stack_align = 16;
|
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let pointer_width = isa.triple().pointer_width().unwrap();
|
||
let word_size = pointer_width.bytes() as usize;
|
||
let reg_type = ir::Type::int(u16::from(pointer_width.bits())).unwrap();
|
||
|
||
let csrs = callee_saved_gprs_used(isa, func);
|
||
|
||
// The reserved stack area is composed of:
|
||
// return address + frame pointer + all callee-saved registers
|
||
//
|
||
// Pushing the return address is an implicit function of the `call`
|
||
// instruction. Each of the others we will then push explicitly. Then we
|
||
// will adjust the stack pointer to make room for the rest of the required
|
||
// space for this frame.
|
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let csr_stack_size = ((csrs.iter(GPR).len() + 2) * word_size) as i32;
|
||
func.create_stack_slot(ir::StackSlotData {
|
||
kind: ir::StackSlotKind::IncomingArg,
|
||
size: csr_stack_size as u32,
|
||
offset: Some(-csr_stack_size),
|
||
});
|
||
|
||
let total_stack_size = layout_stack(&mut func.stack_slots, stack_align)? as i32;
|
||
let local_stack_size = i64::from(total_stack_size - csr_stack_size);
|
||
|
||
// Add CSRs to function signature
|
||
let fp_arg = ir::AbiParam::special_reg(
|
||
reg_type,
|
||
ir::ArgumentPurpose::FramePointer,
|
||
RU::rbp as RegUnit,
|
||
);
|
||
func.signature.params.push(fp_arg);
|
||
func.signature.returns.push(fp_arg);
|
||
|
||
for csr in csrs.iter(GPR) {
|
||
let csr_arg = ir::AbiParam::special_reg(reg_type, ir::ArgumentPurpose::CalleeSaved, csr);
|
||
func.signature.params.push(csr_arg);
|
||
func.signature.returns.push(csr_arg);
|
||
}
|
||
|
||
// Set up the cursor and insert the prologue
|
||
let entry_ebb = func.layout.entry_block().expect("missing entry block");
|
||
let mut pos = EncCursor::new(func, isa).at_first_insertion_point(entry_ebb);
|
||
insert_common_prologue(&mut pos, local_stack_size, reg_type, &csrs, isa);
|
||
|
||
// Reset the cursor and insert the epilogue
|
||
let mut pos = pos.at_position(CursorPosition::Nowhere);
|
||
insert_common_epilogues(&mut pos, local_stack_size, reg_type, &csrs);
|
||
|
||
Ok(())
|
||
}
|
||
|
||
/// Insert the prologue for a given function.
|
||
/// This is used by common calling conventions such as System V.
|
||
fn insert_common_prologue(
|
||
pos: &mut EncCursor,
|
||
stack_size: i64,
|
||
reg_type: ir::types::Type,
|
||
csrs: &RegisterSet,
|
||
isa: &TargetIsa,
|
||
) {
|
||
if stack_size > 0 {
|
||
// Check if there is a special stack limit parameter. If so insert stack check.
|
||
if let Some(stack_limit_arg) = pos.func.special_param(ArgumentPurpose::StackLimit) {
|
||
// Total stack size is the size of all stack area used by the function, including
|
||
// pushed CSRs, frame pointer.
|
||
// Also, the size of a return address, implicitly pushed by a x86 `call` instruction,
|
||
// also should be accounted for.
|
||
// TODO: Check if the function body actually contains a `call` instruction.
|
||
let word_size = isa.pointer_bytes();
|
||
let total_stack_size = (csrs.iter(GPR).len() + 1 + 1) as i64 * word_size as i64;
|
||
|
||
insert_stack_check(pos, total_stack_size, stack_limit_arg);
|
||
}
|
||
}
|
||
|
||
// Append param to entry EBB
|
||
let ebb = pos.current_ebb().expect("missing ebb under cursor");
|
||
let fp = pos.func.dfg.append_ebb_param(ebb, reg_type);
|
||
pos.func.locations[fp] = ir::ValueLoc::Reg(RU::rbp as RegUnit);
|
||
|
||
pos.ins().x86_push(fp);
|
||
pos.ins()
|
||
.copy_special(RU::rsp as RegUnit, RU::rbp as RegUnit);
|
||
|
||
for reg in csrs.iter(GPR) {
|
||
// Append param to entry EBB
|
||
let csr_arg = pos.func.dfg.append_ebb_param(ebb, reg_type);
|
||
|
||
// Assign it a location
|
||
pos.func.locations[csr_arg] = ir::ValueLoc::Reg(reg);
|
||
|
||
// Remember it so we can push it momentarily
|
||
pos.ins().x86_push(csr_arg);
|
||
}
|
||
|
||
// Allocate stack frame storage.
|
||
if stack_size > 0 {
|
||
if isa.flags().probestack_enabled()
|
||
&& stack_size > (1 << isa.flags().probestack_size_log2())
|
||
{
|
||
// Emit a stack probe.
|
||
let rax = RU::rax as RegUnit;
|
||
let rax_val = ir::ValueLoc::Reg(rax);
|
||
|
||
// The probestack function expects its input in %rax.
|
||
let arg = pos.ins().iconst(reg_type, stack_size);
|
||
pos.func.locations[arg] = rax_val;
|
||
|
||
// Call the probestack function.
|
||
let callee = get_probestack_funcref(pos.func, reg_type, rax, isa);
|
||
|
||
// Make the call.
|
||
let call = if !isa.flags().is_pic()
|
||
&& isa.triple().pointer_width().unwrap() == PointerWidth::U64
|
||
&& !pos.func.dfg.ext_funcs[callee].colocated
|
||
{
|
||
// 64-bit non-PIC non-colocated calls need to be legalized to call_indirect.
|
||
// Use r11 as it may be clobbered under all supported calling conventions.
|
||
let r11 = RU::r11 as RegUnit;
|
||
let sig = pos.func.dfg.ext_funcs[callee].signature;
|
||
let addr = pos.ins().func_addr(reg_type, callee);
|
||
pos.func.locations[addr] = ir::ValueLoc::Reg(r11);
|
||
pos.ins().call_indirect(sig, addr, &[arg])
|
||
} else {
|
||
// Otherwise just do a normal call.
|
||
pos.ins().call(callee, &[arg])
|
||
};
|
||
|
||
// If the probestack function doesn't adjust sp, do it ourselves.
|
||
if !isa.flags().probestack_func_adjusts_sp() {
|
||
let result = pos.func.dfg.inst_results(call)[0];
|
||
pos.func.locations[result] = rax_val;
|
||
pos.ins().adjust_sp_down(result);
|
||
}
|
||
} else {
|
||
// Simply decrement the stack pointer.
|
||
pos.ins().adjust_sp_down_imm(Imm64::new(stack_size));
|
||
}
|
||
}
|
||
}
|
||
|
||
/// Insert a check that generates a trap if the stack pointer goes
|
||
/// below a value in `stack_limit_arg`.
|
||
fn insert_stack_check(pos: &mut EncCursor, stack_size: i64, stack_limit_arg: ir::Value) {
|
||
use ir::condcodes::IntCC;
|
||
|
||
// Copy `stack_limit_arg` into a %rax and use it for calculating
|
||
// a SP threshold.
|
||
let stack_limit_copy = pos.ins().copy(stack_limit_arg);
|
||
pos.func.locations[stack_limit_copy] = ir::ValueLoc::Reg(RU::rax as RegUnit);
|
||
let sp_threshold = pos.ins().iadd_imm(stack_limit_copy, stack_size);
|
||
pos.func.locations[sp_threshold] = ir::ValueLoc::Reg(RU::rax as RegUnit);
|
||
|
||
// If the stack pointer currently reaches the SP threshold or below it then after opening
|
||
// the current stack frame, the current stack pointer will reach the limit.
|
||
let cflags = pos.ins().ifcmp_sp(sp_threshold);
|
||
pos.func.locations[cflags] = ir::ValueLoc::Reg(RU::rflags as RegUnit);
|
||
pos.ins().trapif(
|
||
IntCC::UnsignedGreaterThanOrEqual,
|
||
cflags,
|
||
ir::TrapCode::StackOverflow,
|
||
);
|
||
}
|
||
|
||
/// Find all `return` instructions and insert epilogues before them.
|
||
fn insert_common_epilogues(
|
||
pos: &mut EncCursor,
|
||
stack_size: i64,
|
||
reg_type: ir::types::Type,
|
||
csrs: &RegisterSet,
|
||
) {
|
||
while let Some(ebb) = pos.next_ebb() {
|
||
pos.goto_last_inst(ebb);
|
||
if let Some(inst) = pos.current_inst() {
|
||
if pos.func.dfg[inst].opcode().is_return() {
|
||
insert_common_epilogue(inst, stack_size, pos, reg_type, csrs);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
|
||
/// Insert an epilogue given a specific `return` instruction.
|
||
/// This is used by common calling conventions such as System V.
|
||
fn insert_common_epilogue(
|
||
inst: ir::Inst,
|
||
stack_size: i64,
|
||
pos: &mut EncCursor,
|
||
reg_type: ir::types::Type,
|
||
csrs: &RegisterSet,
|
||
) {
|
||
if stack_size > 0 {
|
||
pos.ins().adjust_sp_up_imm(Imm64::new(stack_size));
|
||
}
|
||
|
||
// Pop all the callee-saved registers, stepping backward each time to
|
||
// preserve the correct order.
|
||
let fp_ret = pos.ins().x86_pop(reg_type);
|
||
pos.prev_inst();
|
||
|
||
pos.func.locations[fp_ret] = ir::ValueLoc::Reg(RU::rbp as RegUnit);
|
||
pos.func.dfg.append_inst_arg(inst, fp_ret);
|
||
|
||
for reg in csrs.iter(GPR) {
|
||
let csr_ret = pos.ins().x86_pop(reg_type);
|
||
pos.prev_inst();
|
||
|
||
pos.func.locations[csr_ret] = ir::ValueLoc::Reg(reg);
|
||
pos.func.dfg.append_inst_arg(inst, csr_ret);
|
||
}
|
||
}
|