Sam Parker d307a4ab9a [AArch64] Improve AtomicRMWLoop (#3839) ...

Add more tests, use accurate disassembly, respect data sizes and
simplify the Xchg implementation.

Copyright (c) 2022, Arm Limited

2022-02-23 10:47:59 -08:00

..

unwind

Cranelift: ensure ISA level needed for SIMD is present when SIMD is enabled. (#3816)

2022-02-16 17:29:30 -08:00

args.rs

aarch64: Migrate iadd and isub to ISLE

2021-11-19 06:51:38 -08:00

emit_tests.rs

[AArch64] Improve AtomicRMWLoop (#3839)

2022-02-23 10:47:59 -08:00

emit.rs

[AArch64] Improve AtomicRMWLoop (#3839)

2022-02-23 10:47:59 -08:00

imms.rs

aarch64: Translate rot{r,l} to ISLE (#3614)

2021-12-17 12:37:17 -06:00

mod.rs

[AArch64] Improve AtomicRMWLoop (#3839)

2022-02-23 10:47:59 -08:00

regs.rs

Fix AArch64 ABI to respect half-caller-save, half-callee-save vec regs.

2020-10-06 14:44:02 -07:00

unwind.rs

Rework/simplify unwind infrastructure and implement Windows unwind.

2021-03-11 20:03:52 -08:00