Jakob Stoklund Olesen d2ddc700a8 Add the br_icmp instruction. ...

This instruction behaves like icmp fused with brnz, and it can be used
to represent fused compare+branch instruction on Intel when optimizing
for macro-op fusion.

RISC-V provides compare-and-branch instructions directly, and it is
needed there too.

2017-04-03 15:04:42 -07:00

..

.gitignore

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

compare-llvm.rst

Fix a few typos in the docs;

2016-10-28 11:31:22 -07:00

conf.py

Move the 'meta' dir to 'lib/cretonne/meta'.

2016-10-17 14:19:23 -07:00

cton_domain.py

Use the right operand when documenting type variable inference.

2017-04-03 09:56:47 -07:00

cton_lexer.py

Add a Cretonne testing guide.

2016-09-23 11:37:40 -07:00

example.c

Update language reference.

2016-01-21 14:25:16 -08:00

example.cton

Move entry_block() into Layout.

2016-07-22 10:06:51 -07:00

index.rst

Start a design document for the Cretonne register allocator.

2016-11-21 17:00:16 -08:00

langref.rst

Add the br_icmp instruction.

2017-04-03 15:04:42 -07:00

make.bat

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

Makefile

Add a section about implementation limits.

2017-02-24 11:08:15 -08:00

metaref.rst

Add operand register constraints.

2017-01-25 13:35:18 -08:00

regalloc.rst

Fix some typos in the documentation

2017-01-27 09:51:22 -08:00

testing.rst

Allow for unencoded instructions in the binemit tests.

2017-03-29 09:55:49 -07:00