377 lines
16 KiB
Plaintext
377 lines
16 KiB
Plaintext
; Binary emission of 32-bit floating point code.
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test binemit
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isa intel has_sse2
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32-float.cton | llvm-mc -show-encoding -triple=i386
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;
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function %F32() {
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ss0 = incoming_arg 8, offset 0
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ss1 = incoming_arg 1024, offset -1024
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ss2 = incoming_arg 1024, offset -2048
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ss3 = incoming_arg 8, offset -2056
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ebb0:
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[-,%rcx] v0 = iconst.i32 1
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[-,%rsi] v1 = iconst.i32 2
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; asm: cvtsi2ss %ecx, %xmm5
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[-,%xmm5] v10 = fcvt_from_sint.f32 v0 ; bin: f3 0f 2a e9
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; asm: cvtsi2ss %esi, %xmm2
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[-,%xmm2] v11 = fcvt_from_sint.f32 v1 ; bin: f3 0f 2a d6
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; asm: cvtss2sd %xmm2, %xmm5
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[-,%xmm5] v12 = fpromote.f64 v11 ; bin: f3 0f 5a ea
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; asm: cvtss2sd %xmm5, %xmm2
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[-,%xmm2] v13 = fpromote.f64 v10 ; bin: f3 0f 5a d5
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; asm: movd %ecx, %xmm5
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[-,%xmm5] v14 = bitcast.f32 v0 ; bin: 66 0f 6e e9
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; asm: movd %esi, %xmm2
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[-,%xmm2] v15 = bitcast.f32 v1 ; bin: 66 0f 6e d6
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; asm: movd %xmm5, %ecx
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[-,%rcx] v16 = bitcast.i32 v10 ; bin: 66 0f 7e e9
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; asm: movd %xmm2, %esi
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[-,%rsi] v17 = bitcast.i32 v11 ; bin: 66 0f 7e d6
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; asm: movaps %xmm2, %xmm5
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[-,%xmm5] v18 = copy v11 ; bin: 0f 28 ea
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; asm: movaps %xmm5, %xmm2
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[-,%xmm2] v19 = copy v10 ; bin: 0f 28 d5
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; Binary arithmetic.
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; asm: addss %xmm2, %xmm5
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[-,%xmm5] v20 = fadd v10, v11 ; bin: f3 0f 58 ea
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; asm: addss %xmm5, %xmm2
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[-,%xmm2] v21 = fadd v11, v10 ; bin: f3 0f 58 d5
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; asm: subss %xmm2, %xmm5
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[-,%xmm5] v22 = fsub v10, v11 ; bin: f3 0f 5c ea
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; asm: subss %xmm5, %xmm2
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[-,%xmm2] v23 = fsub v11, v10 ; bin: f3 0f 5c d5
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; asm: mulss %xmm2, %xmm5
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[-,%xmm5] v24 = fmul v10, v11 ; bin: f3 0f 59 ea
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; asm: mulss %xmm5, %xmm2
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[-,%xmm2] v25 = fmul v11, v10 ; bin: f3 0f 59 d5
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; asm: divss %xmm2, %xmm5
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[-,%xmm5] v26 = fdiv v10, v11 ; bin: f3 0f 5e ea
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; asm: divss %xmm5, %xmm2
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[-,%xmm2] v27 = fdiv v11, v10 ; bin: f3 0f 5e d5
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; Bitwise ops.
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; We use the *ps SSE instructions for everything because they are smaller.
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; asm: andps %xmm2, %xmm5
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[-,%xmm5] v30 = band v10, v11 ; bin: 0f 54 ea
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; asm: andps %xmm5, %xmm2
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[-,%xmm2] v31 = band v11, v10 ; bin: 0f 54 d5
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; asm: andnps %xmm2, %xmm5
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[-,%xmm5] v32 = band_not v10, v11 ; bin: 0f 55 ea
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; asm: andnps %xmm5, %xmm2
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[-,%xmm2] v33 = band_not v11, v10 ; bin: 0f 55 d5
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; asm: orps %xmm2, %xmm5
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[-,%xmm5] v34 = bor v10, v11 ; bin: 0f 56 ea
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; asm: orps %xmm5, %xmm2
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[-,%xmm2] v35 = bor v11, v10 ; bin: 0f 56 d5
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; asm: xorps %xmm2, %xmm5
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[-,%xmm5] v36 = bxor v10, v11 ; bin: 0f 57 ea
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; asm: xorps %xmm5, %xmm2
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[-,%xmm2] v37 = bxor v11, v10 ; bin: 0f 57 d5
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; Unary arithmetic.
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; asm: sqrtss %xmm5, %xmm2
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[-,%xmm2] v50 = sqrt v10 ; bin: f3 0f 51 d5
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; asm: sqrtss %xmm2, %xmm5
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[-,%xmm5] v51 = sqrt v11 ; bin: f3 0f 51 ea
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; asm: roundss $0, %xmm5, %xmm4
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[-,%xmm4] v52 = nearest v10 ; bin: 66 0f 3a 0a e5 00
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; asm: roundss $0, %xmm2, %xmm5
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[-,%xmm5] v53 = nearest v11 ; bin: 66 0f 3a 0a ea 00
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; asm: roundss $0, %xmm5, %xmm2
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[-,%xmm2] v54 = nearest v10 ; bin: 66 0f 3a 0a d5 00
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; asm: roundss $1, %xmm5, %xmm4
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[-,%xmm4] v55 = floor v10 ; bin: 66 0f 3a 0a e5 01
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; asm: roundss $1, %xmm2, %xmm5
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[-,%xmm5] v56 = floor v11 ; bin: 66 0f 3a 0a ea 01
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; asm: roundss $1, %xmm5, %xmm2
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[-,%xmm2] v57 = floor v10 ; bin: 66 0f 3a 0a d5 01
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; asm: roundss $2, %xmm5, %xmm4
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[-,%xmm4] v58 = ceil v10 ; bin: 66 0f 3a 0a e5 02
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; asm: roundss $2, %xmm2, %xmm5
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[-,%xmm5] v59 = ceil v11 ; bin: 66 0f 3a 0a ea 02
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; asm: roundss $2, %xmm5, %xmm2
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[-,%xmm2] v60 = ceil v10 ; bin: 66 0f 3a 0a d5 02
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; asm: roundss $3, %xmm5, %xmm4
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[-,%xmm4] v61 = trunc v10 ; bin: 66 0f 3a 0a e5 03
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; asm: roundss $3, %xmm2, %xmm5
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[-,%xmm5] v62 = trunc v11 ; bin: 66 0f 3a 0a ea 03
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; asm: roundss $3, %xmm5, %xmm2
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[-,%xmm2] v63 = trunc v10 ; bin: 66 0f 3a 0a d5 03
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; Load/Store
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; asm: movd (%ecx), %xmm5
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[-,%xmm5] v100 = load.f32 v0 ; bin: 66 0f 6e 29
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; asm: movd (%esi), %xmm2
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[-,%xmm2] v101 = load.f32 v1 ; bin: 66 0f 6e 16
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; asm: movd 50(%ecx), %xmm5
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[-,%xmm5] v110 = load.f32 v0+50 ; bin: 66 0f 6e 69 32
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; asm: movd -50(%esi), %xmm2
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[-,%xmm2] v111 = load.f32 v1-50 ; bin: 66 0f 6e 56 ce
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; asm: movd 10000(%ecx), %xmm5
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[-,%xmm5] v120 = load.f32 v0+10000 ; bin: 66 0f 6e a9 00002710
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; asm: movd -10000(%esi), %xmm2
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[-,%xmm2] v121 = load.f32 v1-10000 ; bin: 66 0f 6e 96 ffffd8f0
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; asm: movd %xmm5, (%ecx)
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[-] store.f32 v100, v0 ; bin: 66 0f 7e 29
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; asm: movd %xmm2, (%esi)
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[-] store.f32 v101, v1 ; bin: 66 0f 7e 16
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; asm: movd %xmm5, 50(%ecx)
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[-] store.f32 v100, v0+50 ; bin: 66 0f 7e 69 32
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; asm: movd %xmm2, -50(%esi)
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[-] store.f32 v101, v1-50 ; bin: 66 0f 7e 56 ce
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; asm: movd %xmm5, 10000(%ecx)
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[-] store.f32 v100, v0+10000 ; bin: 66 0f 7e a9 00002710
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; asm: movd %xmm2, -10000(%esi)
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[-] store.f32 v101, v1-10000 ; bin: 66 0f 7e 96 ffffd8f0
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; Spill / Fill.
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; asm: movd %xmm5, 1032(%esp)
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[-,ss1] v200 = spill v100 ; bin: 66 0f 7e ac 24 00000408
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; asm: movd %xmm2, 1032(%esp)
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[-,ss1] v201 = spill v101 ; bin: 66 0f 7e 94 24 00000408
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; asm: movd 1032(%esp), %xmm5
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[-,%xmm5] v210 = fill v200 ; bin: 66 0f 6e ac 24 00000408
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; asm: movd 1032(%esp), %xmm2
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[-,%xmm2] v211 = fill v201 ; bin: 66 0f 6e 94 24 00000408
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; Comparisons.
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;
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; Only `supported_floatccs` are tested here. Others are handled by
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; legalization paterns.
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; asm: ucomiss %xmm2, %xmm5
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; asm: setnp %bl
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[-,%rbx] v300 = fcmp ord v10, v11 ; bin: 0f 2e ea 0f 9b c3
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; asm: ucomiss %xmm5, %xmm2
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; asm: setp %bl
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[-,%rbx] v301 = fcmp uno v11, v10 ; bin: 0f 2e d5 0f 9a c3
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; asm: ucomiss %xmm2, %xmm5
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; asm: setne %dl
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[-,%rdx] v302 = fcmp one v10, v11 ; bin: 0f 2e ea 0f 95 c2
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; asm: ucomiss %xmm5, %xmm2
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; asm: sete %dl
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[-,%rdx] v303 = fcmp ueq v11, v10 ; bin: 0f 2e d5 0f 94 c2
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; asm: ucomiss %xmm2, %xmm5
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; asm: seta %bl
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[-,%rbx] v304 = fcmp gt v10, v11 ; bin: 0f 2e ea 0f 97 c3
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; asm: ucomiss %xmm5, %xmm2
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; asm: setae %bl
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[-,%rbx] v305 = fcmp ge v11, v10 ; bin: 0f 2e d5 0f 93 c3
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; asm: ucomiss %xmm2, %xmm5
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; asm: setb %dl
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[-,%rdx] v306 = fcmp ult v10, v11 ; bin: 0f 2e ea 0f 92 c2
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; asm: ucomiss %xmm5, %xmm2
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; asm: setbe %dl
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[-,%rdx] v307 = fcmp ule v11, v10 ; bin: 0f 2e d5 0f 96 c2
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return
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}
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function %F64() {
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ss0 = incoming_arg 8, offset 0
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ss1 = incoming_arg 1024, offset -1024
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ss2 = incoming_arg 1024, offset -2048
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ss3 = incoming_arg 8, offset -2056
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ebb0:
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[-,%rcx] v0 = iconst.i32 1
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[-,%rsi] v1 = iconst.i32 2
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; asm: cvtsi2sd %ecx, %xmm5
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[-,%xmm5] v10 = fcvt_from_sint.f64 v0 ; bin: f2 0f 2a e9
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; asm: cvtsi2sd %esi, %xmm2
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[-,%xmm2] v11 = fcvt_from_sint.f64 v1 ; bin: f2 0f 2a d6
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; asm: cvtsd2ss %xmm2, %xmm5
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[-,%xmm5] v12 = fdemote.f32 v11 ; bin: f2 0f 5a ea
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; asm: cvtsd2ss %xmm5, %xmm2
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[-,%xmm2] v13 = fdemote.f32 v10 ; bin: f2 0f 5a d5
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; No i64 <-> f64 bitcasts in 32-bit mode.
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; asm: movaps %xmm2, %xmm5
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[-,%xmm5] v18 = copy v11 ; bin: 0f 28 ea
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; asm: movaps %xmm5, %xmm2
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[-,%xmm2] v19 = copy v10 ; bin: 0f 28 d5
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; Binary arithmetic.
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; asm: addsd %xmm2, %xmm5
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[-,%xmm5] v20 = fadd v10, v11 ; bin: f2 0f 58 ea
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; asm: addsd %xmm5, %xmm2
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[-,%xmm2] v21 = fadd v11, v10 ; bin: f2 0f 58 d5
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; asm: subsd %xmm2, %xmm5
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[-,%xmm5] v22 = fsub v10, v11 ; bin: f2 0f 5c ea
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; asm: subsd %xmm5, %xmm2
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[-,%xmm2] v23 = fsub v11, v10 ; bin: f2 0f 5c d5
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; asm: mulsd %xmm2, %xmm5
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[-,%xmm5] v24 = fmul v10, v11 ; bin: f2 0f 59 ea
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; asm: mulsd %xmm5, %xmm2
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[-,%xmm2] v25 = fmul v11, v10 ; bin: f2 0f 59 d5
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; asm: divsd %xmm2, %xmm5
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[-,%xmm5] v26 = fdiv v10, v11 ; bin: f2 0f 5e ea
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; asm: divsd %xmm5, %xmm2
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[-,%xmm2] v27 = fdiv v11, v10 ; bin: f2 0f 5e d5
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; Bitwise ops.
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; We use the *ps SSE instructions for everything because they are smaller.
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; asm: andps %xmm2, %xmm5
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[-,%xmm5] v30 = band v10, v11 ; bin: 0f 54 ea
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; asm: andps %xmm5, %xmm2
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[-,%xmm2] v31 = band v11, v10 ; bin: 0f 54 d5
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; asm: andnps %xmm2, %xmm5
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[-,%xmm5] v32 = band_not v10, v11 ; bin: 0f 55 ea
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; asm: andnps %xmm5, %xmm2
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[-,%xmm2] v33 = band_not v11, v10 ; bin: 0f 55 d5
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; asm: orps %xmm2, %xmm5
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[-,%xmm5] v34 = bor v10, v11 ; bin: 0f 56 ea
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; asm: orps %xmm5, %xmm2
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[-,%xmm2] v35 = bor v11, v10 ; bin: 0f 56 d5
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; asm: xorps %xmm2, %xmm5
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[-,%xmm5] v36 = bxor v10, v11 ; bin: 0f 57 ea
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; asm: xorps %xmm5, %xmm2
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[-,%xmm2] v37 = bxor v11, v10 ; bin: 0f 57 d5
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; Unary arithmetic.
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; asm: sqrtsd %xmm5, %xmm2
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[-,%xmm2] v50 = sqrt v10 ; bin: f2 0f 51 d5
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; asm: sqrtsd %xmm2, %xmm5
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[-,%xmm5] v51 = sqrt v11 ; bin: f2 0f 51 ea
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; asm: roundsd $0, %xmm5, %xmm4
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[-,%xmm4] v52 = nearest v10 ; bin: 66 0f 3a 0b e5 00
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; asm: roundsd $0, %xmm2, %xmm5
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[-,%xmm5] v53 = nearest v11 ; bin: 66 0f 3a 0b ea 00
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; asm: roundsd $0, %xmm5, %xmm2
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[-,%xmm2] v54 = nearest v10 ; bin: 66 0f 3a 0b d5 00
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; asm: roundsd $1, %xmm5, %xmm4
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[-,%xmm4] v55 = floor v10 ; bin: 66 0f 3a 0b e5 01
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; asm: roundsd $1, %xmm2, %xmm5
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[-,%xmm5] v56 = floor v11 ; bin: 66 0f 3a 0b ea 01
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; asm: roundsd $1, %xmm5, %xmm2
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[-,%xmm2] v57 = floor v10 ; bin: 66 0f 3a 0b d5 01
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; asm: roundsd $2, %xmm5, %xmm4
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[-,%xmm4] v58 = ceil v10 ; bin: 66 0f 3a 0b e5 02
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; asm: roundsd $2, %xmm2, %xmm5
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[-,%xmm5] v59 = ceil v11 ; bin: 66 0f 3a 0b ea 02
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; asm: roundsd $2, %xmm5, %xmm2
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[-,%xmm2] v60 = ceil v10 ; bin: 66 0f 3a 0b d5 02
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; asm: roundsd $3, %xmm5, %xmm4
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[-,%xmm4] v61 = trunc v10 ; bin: 66 0f 3a 0b e5 03
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; asm: roundsd $3, %xmm2, %xmm5
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[-,%xmm5] v62 = trunc v11 ; bin: 66 0f 3a 0b ea 03
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; asm: roundsd $3, %xmm5, %xmm2
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[-,%xmm2] v63 = trunc v10 ; bin: 66 0f 3a 0b d5 03
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; Load/Store
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; asm: movq (%ecx), %xmm5
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[-,%xmm5] v100 = load.f64 v0 ; bin: f3 0f 7e 29
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; asm: movq (%esi), %xmm2
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[-,%xmm2] v101 = load.f64 v1 ; bin: f3 0f 7e 16
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; asm: movq 50(%ecx), %xmm5
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[-,%xmm5] v110 = load.f64 v0+50 ; bin: f3 0f 7e 69 32
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; asm: movq -50(%esi), %xmm2
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[-,%xmm2] v111 = load.f64 v1-50 ; bin: f3 0f 7e 56 ce
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; asm: movq 10000(%ecx), %xmm5
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[-,%xmm5] v120 = load.f64 v0+10000 ; bin: f3 0f 7e a9 00002710
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; asm: movq -10000(%esi), %xmm2
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[-,%xmm2] v121 = load.f64 v1-10000 ; bin: f3 0f 7e 96 ffffd8f0
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; asm: movq %xmm5, (%ecx)
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[-] store.f64 v100, v0 ; bin: 66 0f d6 29
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; asm: movq %xmm2, (%esi)
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[-] store.f64 v101, v1 ; bin: 66 0f d6 16
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; asm: movq %xmm5, 50(%ecx)
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[-] store.f64 v100, v0+50 ; bin: 66 0f d6 69 32
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; asm: movq %xmm2, -50(%esi)
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[-] store.f64 v101, v1-50 ; bin: 66 0f d6 56 ce
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; asm: movq %xmm5, 10000(%ecx)
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[-] store.f64 v100, v0+10000 ; bin: 66 0f d6 a9 00002710
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; asm: movq %xmm2, -10000(%esi)
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[-] store.f64 v101, v1-10000 ; bin: 66 0f d6 96 ffffd8f0
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; Spill / Fill.
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; asm: movq %xmm5, 1032(%esp)
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[-,ss1] v200 = spill v100 ; bin: 66 0f d6 ac 24 00000408
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; asm: movq %xmm2, 1032(%esp)
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[-,ss1] v201 = spill v101 ; bin: 66 0f d6 94 24 00000408
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; asm: movq 1032(%esp), %xmm5
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[-,%xmm5] v210 = fill v200 ; bin: f3 0f 7e ac 24 00000408
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; asm: movq 1032(%esp), %xmm2
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[-,%xmm2] v211 = fill v201 ; bin: f3 0f 7e 94 24 00000408
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; Comparisons.
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;
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; Only `supported_floatccs` are tested here. Others are handled by
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; legalization paterns.
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; asm: ucomisd %xmm2, %xmm5
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; asm: setnp %bl
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[-,%rbx] v300 = fcmp ord v10, v11 ; bin: 66 0f 2e ea 0f 9b c3
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; asm: ucomisd %xmm5, %xmm2
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; asm: setp %bl
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[-,%rbx] v301 = fcmp uno v11, v10 ; bin: 66 0f 2e d5 0f 9a c3
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; asm: ucomisd %xmm2, %xmm5
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; asm: setne %dl
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[-,%rdx] v302 = fcmp one v10, v11 ; bin: 66 0f 2e ea 0f 95 c2
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; asm: ucomisd %xmm5, %xmm2
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; asm: sete %dl
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[-,%rdx] v303 = fcmp ueq v11, v10 ; bin: 66 0f 2e d5 0f 94 c2
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; asm: ucomisd %xmm2, %xmm5
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; asm: seta %bl
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[-,%rbx] v304 = fcmp gt v10, v11 ; bin: 66 0f 2e ea 0f 97 c3
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; asm: ucomisd %xmm5, %xmm2
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; asm: setae %bl
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[-,%rbx] v305 = fcmp ge v11, v10 ; bin: 66 0f 2e d5 0f 93 c3
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; asm: ucomisd %xmm2, %xmm5
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; asm: setb %dl
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[-,%rdx] v306 = fcmp ult v10, v11 ; bin: 66 0f 2e ea 0f 92 c2
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; asm: ucomisd %xmm5, %xmm2
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; asm: setbe %dl
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[-,%rdx] v307 = fcmp ule v11, v10 ; bin: 66 0f 2e d5 0f 96 c2
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return
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}
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