Jakob Stoklund Olesen 85aab278dd Add RISC-V encodings for b1 copy/spill/fill. ...

We allow b1 values in general purpose registers, so we need to be able
to move them around.

2018-01-16 09:19:22 -08:00

..

arm32

Add register banks for CPU flags to Intel and ARM ISAs.

2017-10-13 14:02:09 -07:00

arm64

Add register banks for CPU flags to Intel and ARM ISAs.

2017-10-13 14:02:09 -07:00

intel

Align IntelGOTPCRel4 with R_X86_64_GOTPCREL.

2017-12-15 16:17:32 -06:00

riscv

Add RISC-V encodings for b1 copy/spill/fill.

2018-01-16 09:19:22 -08:00

__init__.py

Fixed for mypy 0.501.

2017-03-03 09:08:28 -08:00