cd99eee86b
The legalize_signature() function will return ArgumentLoc::Reg arguments that contain a register unit. However, the register also needs to be able to associate a register class with the argument values to fully track the used registers. When values are defined by instructions, the register class is part for the operand constraints for the instruction. For values defined on ABI boundaries like function arguments and return values from a call, the register class is provided by the new regclass_for_abi_type() function. Provide implementations of this function in abi modules of all the targets, even those that don't have a legalize_signature() implementation yet. Since we're adding abi modules to all targets, move the legalize_signature() stubs in there and make the function mandatory in TargetIsa. All targets will eventually need this function.
111 lines
3.6 KiB
Rust
111 lines
3.6 KiB
Rust
//! RISC-V ABI implementation.
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//!
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//! This module implements the RISC-V calling convention through the primary `legalize_signature()`
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//! entry point.
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//!
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//! This doesn't support the soft-float ABI at the moment.
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use abi::{ArgAction, ValueConversion, ArgAssigner, legalize_args};
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use ir::{Signature, Type, ArgumentType, ArgumentLoc, ArgumentExtension, ArgumentPurpose};
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use isa::RegClass;
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use isa::riscv::registers::{GPR, FPR};
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use settings as shared_settings;
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struct Args {
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pointer_bits: u16,
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pointer_bytes: u32,
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pointer_type: Type,
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regs: u32,
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offset: u32,
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}
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impl Args {
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fn new(bits: u16) -> Args {
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Args {
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pointer_bits: bits,
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pointer_bytes: bits as u32 / 8,
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pointer_type: Type::int(bits).unwrap(),
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regs: 0,
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offset: 0,
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}
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}
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}
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impl ArgAssigner for Args {
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fn assign(&mut self, arg: &ArgumentType) -> ArgAction {
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fn align(value: u32, to: u32) -> u32 {
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(value + to - 1) & !(to - 1)
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}
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let ty = arg.value_type;
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// Check for a legal type.
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// RISC-V doesn't have SIMD at all, so break all vectors down.
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if !ty.is_scalar() {
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return ValueConversion::VectorSplit.into();
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}
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// Large integers and booleans are broken down to fit in a register.
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if !ty.is_float() && ty.bits() > self.pointer_bits {
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// Align registers and stack to a multiple of two pointers.
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self.regs = align(self.regs, 2);
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self.offset = align(self.offset, 2 * self.pointer_bytes);
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return ValueConversion::IntSplit.into();
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}
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// Small integers are extended to the size of a pointer register.
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if ty.is_int() && ty.bits() < self.pointer_bits {
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match arg.extension {
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ArgumentExtension::None => {}
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ArgumentExtension::Uext => return ValueConversion::Uext(self.pointer_type).into(),
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ArgumentExtension::Sext => return ValueConversion::Sext(self.pointer_type).into(),
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}
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}
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if self.regs < 8 {
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// Assign to a register.
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let reg = if ty.is_float() {
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FPR.unit(10 + self.regs as usize)
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} else {
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GPR.unit(10 + self.regs as usize)
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};
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self.regs += 1;
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ArgumentLoc::Reg(reg).into()
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} else {
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// Assign a stack location.
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let loc = ArgumentLoc::Stack(self.offset);
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self.offset += self.pointer_bytes;
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loc.into()
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}
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}
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}
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/// Legalize `sig` for RISC-V.
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pub fn legalize_signature(sig: &mut Signature, flags: &shared_settings::Flags, current: bool) {
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let bits = if flags.is_64bit() { 64 } else { 32 };
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let mut args = Args::new(bits);
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legalize_args(&mut sig.argument_types, &mut args);
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let mut rets = Args::new(bits);
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legalize_args(&mut sig.return_types, &mut rets);
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if current {
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let ptr = Type::int(bits).unwrap();
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// Add the link register as an argument and return value.
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//
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// The `jalr` instruction implementing a return can technically accept the return address
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// in any register, but a micro-architecture with a return address predictor will only
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// recognize it as a return if the address is in `x1`.
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let link = ArgumentType::special_reg(ptr, ArgumentPurpose::Link, GPR.unit(1));
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sig.argument_types.push(link);
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sig.return_types.push(link);
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}
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}
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/// Get register class for a type appearing in a legalized signature.
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pub fn regclass_for_abi_type(ty: Type) -> RegClass {
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if ty.is_float() { FPR } else { GPR }
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}
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