228 lines
6.5 KiB
Python
228 lines
6.5 KiB
Python
"""
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Custom legalization patterns for x86.
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"""
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from __future__ import absolute_import
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from cdsl.ast import Var
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from cdsl.xform import Rtl, XFormGroup
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from base.immediates import imm64, intcc, floatcc
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from base import legalize as shared
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from base import instructions as insts
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from . import instructions as x86
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from .defs import ISA
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x86_expand = XFormGroup(
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'x86_expand',
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"""
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Legalize instructions by expansion.
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Use x86-specific instructions if needed.
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""",
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isa=ISA, chain=shared.expand_flags)
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a = Var('a')
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dead = Var('dead')
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x = Var('x')
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xhi = Var('xhi')
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y = Var('y')
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a1 = Var('a1')
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a2 = Var('a2')
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#
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# Division and remainder.
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#
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# The srem expansion requires custom code because srem INT_MIN, -1 is not
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# allowed to trap. The other ops need to check avoid_div_traps.
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x86_expand.custom_legalize(insts.sdiv, 'expand_sdivrem')
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x86_expand.custom_legalize(insts.srem, 'expand_sdivrem')
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x86_expand.custom_legalize(insts.udiv, 'expand_udivrem')
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x86_expand.custom_legalize(insts.urem, 'expand_udivrem')
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#
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# Double length (widening) multiplication
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#
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resLo = Var('resLo')
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resHi = Var('resHi')
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x86_expand.legalize(
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resHi << insts.umulhi(x, y),
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Rtl(
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(resLo, resHi) << x86.umulx(x, y)
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))
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x86_expand.legalize(
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resHi << insts.smulhi(x, y),
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Rtl(
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(resLo, resHi) << x86.smulx(x, y)
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))
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# Floating point condition codes.
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#
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# The 8 condition codes in `supported_floatccs` are directly supported by a
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# `ucomiss` or `ucomisd` instruction. The remaining codes need legalization
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# patterns.
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# Equality needs an explicit `ord` test which checks the parity bit.
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x86_expand.legalize(
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a << insts.fcmp(floatcc.eq, x, y),
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Rtl(
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a1 << insts.fcmp(floatcc.ord, x, y),
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a2 << insts.fcmp(floatcc.ueq, x, y),
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a << insts.band(a1, a2)
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))
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x86_expand.legalize(
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a << insts.fcmp(floatcc.ne, x, y),
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Rtl(
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a1 << insts.fcmp(floatcc.uno, x, y),
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a2 << insts.fcmp(floatcc.one, x, y),
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a << insts.bor(a1, a2)
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))
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# Inequalities that need to be reversed.
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for cc, rev_cc in [
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(floatcc.lt, floatcc.gt),
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(floatcc.le, floatcc.ge),
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(floatcc.ugt, floatcc.ult),
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(floatcc.uge, floatcc.ule)]:
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x86_expand.legalize(
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a << insts.fcmp(cc, x, y),
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Rtl(
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a << insts.fcmp(rev_cc, y, x)
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))
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# We need to modify the CFG for min/max legalization.
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x86_expand.custom_legalize(insts.fmin, 'expand_minmax')
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x86_expand.custom_legalize(insts.fmax, 'expand_minmax')
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# Conversions from unsigned need special handling.
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x86_expand.custom_legalize(insts.fcvt_from_uint, 'expand_fcvt_from_uint')
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# Conversions from float to int can trap.
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x86_expand.custom_legalize(insts.fcvt_to_sint, 'expand_fcvt_to_sint')
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x86_expand.custom_legalize(insts.fcvt_to_uint, 'expand_fcvt_to_uint')
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# Count leading and trailing zeroes, for baseline x86_64
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c_minus_one = Var('c_minus_one')
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c_thirty_one = Var('c_thirty_one')
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c_thirty_two = Var('c_thirty_two')
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c_sixty_three = Var('c_sixty_three')
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c_sixty_four = Var('c_sixty_four')
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index1 = Var('index1')
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r2flags = Var('r2flags')
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index2 = Var('index2')
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x86_expand.legalize(
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a << insts.clz.i64(x),
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Rtl(
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c_minus_one << insts.iconst(imm64(-1)),
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c_sixty_three << insts.iconst(imm64(63)),
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(index1, r2flags) << x86.bsr(x),
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index2 << insts.selectif(intcc.eq, r2flags, c_minus_one, index1),
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a << insts.isub(c_sixty_three, index2),
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))
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x86_expand.legalize(
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a << insts.clz.i32(x),
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Rtl(
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c_minus_one << insts.iconst(imm64(-1)),
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c_thirty_one << insts.iconst(imm64(31)),
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(index1, r2flags) << x86.bsr(x),
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index2 << insts.selectif(intcc.eq, r2flags, c_minus_one, index1),
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a << insts.isub(c_thirty_one, index2),
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))
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x86_expand.legalize(
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a << insts.ctz.i64(x),
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Rtl(
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c_sixty_four << insts.iconst(imm64(64)),
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(index1, r2flags) << x86.bsf(x),
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a << insts.selectif(intcc.eq, r2flags, c_sixty_four, index1),
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))
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x86_expand.legalize(
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a << insts.ctz.i32(x),
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Rtl(
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c_thirty_two << insts.iconst(imm64(32)),
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(index1, r2flags) << x86.bsf(x),
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a << insts.selectif(intcc.eq, r2flags, c_thirty_two, index1),
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))
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# Population count for baseline x86_64
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qv1 = Var('qv1')
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qv3 = Var('qv3')
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qv4 = Var('qv4')
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qv5 = Var('qv5')
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qv6 = Var('qv6')
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qv7 = Var('qv7')
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qv8 = Var('qv8')
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qv9 = Var('qv9')
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qv10 = Var('qv10')
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qv11 = Var('qv11')
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qv12 = Var('qv12')
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qv13 = Var('qv13')
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qv14 = Var('qv14')
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qv15 = Var('qv15')
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qv16 = Var('qv16')
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qc77 = Var('qc77')
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qc0F = Var('qc0F')
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qc01 = Var('qc01')
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x86_expand.legalize(
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qv16 << insts.popcnt.i64(qv1),
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Rtl(
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qv3 << insts.ushr_imm(qv1, imm64(1)),
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qc77 << insts.iconst(imm64(0x7777777777777777)),
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qv4 << insts.band(qv3, qc77),
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qv5 << insts.isub(qv1, qv4),
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qv6 << insts.ushr_imm(qv4, imm64(1)),
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qv7 << insts.band(qv6, qc77),
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qv8 << insts.isub(qv5, qv7),
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qv9 << insts.ushr_imm(qv7, imm64(1)),
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qv10 << insts.band(qv9, qc77),
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qv11 << insts.isub(qv8, qv10),
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qv12 << insts.ushr_imm(qv11, imm64(4)),
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qv13 << insts.iadd(qv11, qv12),
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qc0F << insts.iconst(imm64(0x0F0F0F0F0F0F0F0F)),
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qv14 << insts.band(qv13, qc0F),
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qc01 << insts.iconst(imm64(0x0101010101010101)),
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qv15 << insts.imul(qv14, qc01),
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qv16 << insts.ushr_imm(qv15, imm64(56))
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))
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lv1 = Var('lv1')
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lv3 = Var('lv3')
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lv4 = Var('lv4')
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lv5 = Var('lv5')
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lv6 = Var('lv6')
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lv7 = Var('lv7')
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lv8 = Var('lv8')
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lv9 = Var('lv9')
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lv10 = Var('lv10')
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lv11 = Var('lv11')
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lv12 = Var('lv12')
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lv13 = Var('lv13')
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lv14 = Var('lv14')
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lv15 = Var('lv15')
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lv16 = Var('lv16')
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lc77 = Var('lc77')
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lc0F = Var('lc0F')
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lc01 = Var('lc01')
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x86_expand.legalize(
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lv16 << insts.popcnt.i32(lv1),
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Rtl(
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lv3 << insts.ushr_imm(lv1, imm64(1)),
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lc77 << insts.iconst(imm64(0x77777777)),
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lv4 << insts.band(lv3, lc77),
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lv5 << insts.isub(lv1, lv4),
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lv6 << insts.ushr_imm(lv4, imm64(1)),
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lv7 << insts.band(lv6, lc77),
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lv8 << insts.isub(lv5, lv7),
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lv9 << insts.ushr_imm(lv7, imm64(1)),
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lv10 << insts.band(lv9, lc77),
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lv11 << insts.isub(lv8, lv10),
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lv12 << insts.ushr_imm(lv11, imm64(4)),
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lv13 << insts.iadd(lv11, lv12),
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lc0F << insts.iconst(imm64(0x0F0F0F0F)),
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lv14 << insts.band(lv13, lc0F),
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lc01 << insts.iconst(imm64(0x01010101)),
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lv15 << insts.imul(lv14, lc01),
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lv16 << insts.ushr_imm(lv15, imm64(24))
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))
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