94b51cdb17
This change substitutes the string based emission mechanism with
cranelift-codegen's x64 backend.
This change _does not_:
* Introduce new functionality in terms of supported instructions.
* Change the semantics of the assembler/macroassembler in terms of the logic to
emit instructions.
The most notable differences between this change and the previous version are:
* Handling of shared flags and ISA-specific flags, which for now are left with
the default value.
* Simplification of instruction emission per operand size: previously the
assembler defined different methods depending on the operand size (e.g. `mov`
for 64 bits, and `movl` for 32 bits). This change updates such approach so that
each assembler method takes an operand size as a parameter, reducing duplication
and making the code more concise and easier to integrate with the x64's `Inst` enum.
* Introduction of a disassembler for testing purposes.
As of this change, Winch generates the following code for the following test
programs:
```wat
(module
(export "main" (func $main))
(func $main (result i32)
(i32.const 10)
(i32.const 20)
i32.add
))
```
```asm
0: 55 push rbp
1: 48 89 e5 mov rbp, rsp
4: b8 0a 00 00 00 mov eax, 0xa
9: 83 c0 14 add eax, 0x14
c: 5d pop rbp
d: c3 ret
```
```wat
(module
(export "main" (func $main))
(func $main (result i32)
(local $foo i32)
(local $bar i32)
(i32.const 10)
(local.set $foo)
(i32.const 20)
(local.set $bar)
(local.get $foo)
(local.get $bar)
i32.add
))
```
```asm
0: 55 push rbp
1: 48 89 e5 mov rbp, rsp
4: 48 83 ec 08 sub rsp, 8
8: 48 c7 04 24 00 00 00 00 mov qword ptr [rsp], 0
10: b8 0a 00 00 00 mov eax, 0xa
15: 89 44 24 04 mov dword ptr [rsp + 4], eax
19: b8 14 00 00 00 mov eax, 0x14
1e: 89 04 24 mov dword ptr [rsp], eax
21: 8b 04 24 mov eax, dword ptr [rsp]
24: 8b 4c 24 04 mov ecx, dword ptr [rsp + 4]
28: 01 c1 add ecx, eax
2a: 48 89 c8 mov rax, rcx
2d: 48 83 c4 08 add rsp, 8
31: 5d pop rbp
32: c3 ret
```
```wat
(module
(export "main" (func $main))
(func $main (param i32) (param i32) (result i32)
(local.get 0)
(local.get 1)
i32.add
))
```
```asm
0: 55 push rbp
1: 48 89 e5 mov rbp, rsp
4: 48 83 ec 08 sub rsp, 8
8: 89 7c 24 04 mov dword ptr [rsp + 4], edi
c: 89 34 24 mov dword ptr [rsp], esi
f: 8b 04 24 mov eax, dword ptr [rsp]
12: 8b 4c 24 04 mov ecx, dword ptr [rsp + 4]
16: 01 c1 add ecx, eax
18: 48 89 c8 mov rax, rcx
1b: 48 83 c4 08 add rsp, 8
1f: 5d pop rbp
20: c3 ret
```
73 lines
1.9 KiB
Rust
73 lines
1.9 KiB
Rust
use crate::compiler::Compiler;
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use anyhow::Result;
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use cranelift_codegen::settings;
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use std::sync::Arc;
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use target_lexicon::Triple;
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use wasmtime_environ::{CompilerBuilder, Setting};
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use winch_codegen::isa;
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/// Compiler builder.
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struct Builder {
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/// Target triple.
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triple: Triple,
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/// Shared flags builder.
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shared_flags: settings::Builder,
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/// ISA builder.
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isa_builder: isa::Builder,
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}
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pub fn builder() -> Box<dyn CompilerBuilder> {
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let triple = Triple::host();
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Box::new(Builder {
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triple: triple.clone(),
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shared_flags: settings::builder(),
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// TODO:
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// Either refactor and re-use `cranelift-native::builder()` or come up with a similar
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// mechanism to lookup the host's architecture ISA and infer native flags.
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isa_builder: isa::lookup(triple).expect("host architecture is not supported"),
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})
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}
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impl CompilerBuilder for Builder {
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fn triple(&self) -> &target_lexicon::Triple {
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&self.triple
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}
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fn target(&mut self, target: target_lexicon::Triple) -> Result<()> {
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self.triple = target;
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Ok(())
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}
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fn set(&mut self, _name: &str, _val: &str) -> Result<()> {
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Ok(())
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}
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fn enable(&mut self, _name: &str) -> Result<()> {
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Ok(())
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}
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fn settings(&self) -> Vec<Setting> {
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vec![]
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}
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fn build(&self) -> Result<Box<dyn wasmtime_environ::Compiler>> {
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let flags = settings::Flags::new(self.shared_flags.clone());
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Ok(Box::new(Compiler::new(
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self.isa_builder.clone().build(flags)?,
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)))
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}
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fn enable_incremental_compilation(
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&mut self,
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_cache_store: Arc<dyn wasmtime_environ::CacheStore>,
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) {
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todo!()
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}
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}
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impl std::fmt::Debug for Builder {
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fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
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write!(f, "Builder: {{ triple: {:?} }}", self.triple())
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}
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}
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