cc073593a4
As a follow-up to #5780, disassemble the regions identified by bb_starts, falling back on disassembling the whole buffer. This ensures that instructions like br_table that introduce a lot of constants don't throw off capstone for the remainder of the function. --------- Co-authored-by: Jamey Sharp <jamey@minilop.net>
768 lines
13 KiB
Plaintext
768 lines
13 KiB
Plaintext
test compile precise-output
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target aarch64 has_lse
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function %atomic_rmw_add_i64(i64, i64) {
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block0(v0: i64, v1: i64):
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v2 = atomic_rmw.i64 add v0, v1
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return
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}
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; VCode:
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; block0:
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; ldaddal x1, x3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldaddal x1, x3, [x0]
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; ret
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function %atomic_rmw_add_i32(i64, i32) {
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block0(v0: i64, v1: i32):
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v2 = atomic_rmw.i32 add v0, v1
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return
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}
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; VCode:
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; block0:
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; ldaddal w1, w3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldaddal w1, w3, [x0]
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; ret
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function %atomic_rmw_add_i16(i64, i16) {
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block0(v0: i64, v1: i16):
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v2 = atomic_rmw.i16 add v0, v1
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return
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}
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; VCode:
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; block0:
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; ldaddalh w1, w3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldaddalh w1, w3, [x0]
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; ret
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function %atomic_rmw_add_i8(i64, i8) {
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block0(v0: i64, v1: i8):
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v2 = atomic_rmw.i8 add v0, v1
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return
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}
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; VCode:
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; block0:
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; ldaddalb w1, w3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldaddalb w1, w3, [x0]
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; ret
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function %atomic_rmw_sub_i64(i64, i64) {
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block0(v0: i64, v1: i64):
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v2 = atomic_rmw.i64 sub v0, v1
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return
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}
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; VCode:
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; block0:
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; sub x3, xzr, x1
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; ldaddal x3, x5, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; neg x3, x1
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; ldaddal x3, x5, [x0]
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; ret
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function %atomic_rmw_sub_i32(i64, i32) {
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block0(v0: i64, v1: i32):
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v2 = atomic_rmw.i32 sub v0, v1
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return
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}
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; VCode:
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; block0:
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; sub w3, wzr, w1
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; ldaddal w3, w5, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; neg w3, w1
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; ldaddal w3, w5, [x0]
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; ret
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function %atomic_rmw_sub_i16(i64, i16) {
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block0(v0: i64, v1: i16):
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v2 = atomic_rmw.i16 sub v0, v1
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return
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}
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; VCode:
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; block0:
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; sub w3, wzr, w1
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; ldaddalh w3, w5, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; neg w3, w1
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; ldaddalh w3, w5, [x0]
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; ret
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function %atomic_rmw_sub_i8(i64, i8) {
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block0(v0: i64, v1: i8):
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v2 = atomic_rmw.i8 sub v0, v1
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return
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}
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; VCode:
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; block0:
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; sub w3, wzr, w1
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; ldaddalb w3, w5, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; neg w3, w1
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; ldaddalb w3, w5, [x0]
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; ret
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function %atomic_rmw_and_i64(i64, i64) {
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block0(v0: i64, v1: i64):
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v2 = atomic_rmw.i64 and v0, v1
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return
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}
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; VCode:
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; block0:
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; eon x3, x1, xzr
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; ldclral x3, x5, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; eon x3, x1, xzr
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; ldclral x3, x5, [x0]
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; ret
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function %atomic_rmw_and_i32(i64, i32) {
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block0(v0: i64, v1: i32):
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v2 = atomic_rmw.i32 and v0, v1
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return
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}
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; VCode:
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; block0:
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; eon w3, w1, wzr
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; ldclral w3, w5, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; eon w3, w1, wzr
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; ldclral w3, w5, [x0]
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; ret
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function %atomic_rmw_and_i16(i64, i16) {
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block0(v0: i64, v1: i16):
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v2 = atomic_rmw.i16 and v0, v1
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return
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}
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; VCode:
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; block0:
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; eon w3, w1, wzr
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; ldclralh w3, w5, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; eon w3, w1, wzr
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; ldclralh w3, w5, [x0]
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; ret
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function %atomic_rmw_and_i8(i64, i8) {
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block0(v0: i64, v1: i8):
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v2 = atomic_rmw.i8 and v0, v1
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return
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}
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; VCode:
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; block0:
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; eon w3, w1, wzr
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; ldclralb w3, w5, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; eon w3, w1, wzr
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; ldclralb w3, w5, [x0]
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; ret
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function %atomic_rmw_nand_i64(i64, i64) {
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block0(v0: i64, v1: i64):
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v2 = atomic_rmw.i64 nand v0, v1
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return
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}
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; VCode:
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; str x28, [sp, #-16]!
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; stp x26, x27, [sp, #-16]!
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; stp x24, x25, [sp, #-16]!
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; block0:
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; mov x25, x0
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; mov x26, x1
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; atomic_rmw_loop_nand_64 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28
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; ldp x24, x25, [sp], #16
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; ldp x26, x27, [sp], #16
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; ldr x28, [sp], #16
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; ldp fp, lr, [sp], #16
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stp x29, x30, [sp, #-0x10]!
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; mov x29, sp
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; str x28, [sp, #-0x10]!
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; stp x26, x27, [sp, #-0x10]!
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; stp x24, x25, [sp, #-0x10]!
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; block1: ; offset 0x14
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; mov x25, x0
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; mov x26, x1
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; ldaxr x27, [x25]
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; and x28, x27, x26
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; mvn x28, x28
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; stlxr w24, x28, [x25]
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; cbnz x24, #0x1c
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; ldp x24, x25, [sp], #0x10
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; ldp x26, x27, [sp], #0x10
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; ldr x28, [sp], #0x10
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; ldp x29, x30, [sp], #0x10
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; ret
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function %atomic_rmw_nand_i32(i64, i32) {
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block0(v0: i64, v1: i32):
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v2 = atomic_rmw.i32 nand v0, v1
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return
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}
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; VCode:
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; str x28, [sp, #-16]!
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; stp x26, x27, [sp, #-16]!
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; stp x24, x25, [sp, #-16]!
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; block0:
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; mov x25, x0
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; mov x26, x1
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; atomic_rmw_loop_nand_32 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28
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; ldp x24, x25, [sp], #16
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; ldp x26, x27, [sp], #16
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; ldr x28, [sp], #16
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; ldp fp, lr, [sp], #16
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stp x29, x30, [sp, #-0x10]!
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; mov x29, sp
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; str x28, [sp, #-0x10]!
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; stp x26, x27, [sp, #-0x10]!
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; stp x24, x25, [sp, #-0x10]!
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; block1: ; offset 0x14
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; mov x25, x0
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; mov x26, x1
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; ldaxr w27, [x25]
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; and w28, w27, w26
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; mvn w28, w28
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; stlxr w24, w28, [x25]
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; cbnz x24, #0x1c
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; ldp x24, x25, [sp], #0x10
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; ldp x26, x27, [sp], #0x10
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; ldr x28, [sp], #0x10
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; ldp x29, x30, [sp], #0x10
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; ret
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function %atomic_rmw_nand_i16(i64, i16) {
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block0(v0: i64, v1: i16):
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v2 = atomic_rmw.i16 nand v0, v1
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return
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}
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; VCode:
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; str x28, [sp, #-16]!
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; stp x26, x27, [sp, #-16]!
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; stp x24, x25, [sp, #-16]!
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; block0:
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; mov x25, x0
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; mov x26, x1
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; atomic_rmw_loop_nand_16 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28
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; ldp x24, x25, [sp], #16
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; ldp x26, x27, [sp], #16
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; ldr x28, [sp], #16
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; ldp fp, lr, [sp], #16
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stp x29, x30, [sp, #-0x10]!
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; mov x29, sp
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; str x28, [sp, #-0x10]!
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; stp x26, x27, [sp, #-0x10]!
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; stp x24, x25, [sp, #-0x10]!
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; block1: ; offset 0x14
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; mov x25, x0
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; mov x26, x1
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; ldaxrh w27, [x25]
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; and w28, w27, w26
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; mvn w28, w28
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; stlxrh w24, w28, [x25]
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; cbnz x24, #0x1c
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; ldp x24, x25, [sp], #0x10
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; ldp x26, x27, [sp], #0x10
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; ldr x28, [sp], #0x10
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; ldp x29, x30, [sp], #0x10
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; ret
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function %atomic_rmw_nand_i8(i64, i8) {
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block0(v0: i64, v1: i8):
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v2 = atomic_rmw.i8 nand v0, v1
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return
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}
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; VCode:
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; str x28, [sp, #-16]!
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; stp x26, x27, [sp, #-16]!
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; stp x24, x25, [sp, #-16]!
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; block0:
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; mov x25, x0
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; mov x26, x1
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; atomic_rmw_loop_nand_8 addr=x25 operand=x26 oldval=x27 scratch1=x24 scratch2=x28
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; ldp x24, x25, [sp], #16
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; ldp x26, x27, [sp], #16
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; ldr x28, [sp], #16
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; ldp fp, lr, [sp], #16
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stp x29, x30, [sp, #-0x10]!
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; mov x29, sp
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; str x28, [sp, #-0x10]!
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; stp x26, x27, [sp, #-0x10]!
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; stp x24, x25, [sp, #-0x10]!
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; block1: ; offset 0x14
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; mov x25, x0
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; mov x26, x1
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; ldaxrb w27, [x25]
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; and w28, w27, w26
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; mvn w28, w28
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; stlxrb w24, w28, [x25]
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; cbnz x24, #0x1c
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; ldp x24, x25, [sp], #0x10
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; ldp x26, x27, [sp], #0x10
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; ldr x28, [sp], #0x10
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; ldp x29, x30, [sp], #0x10
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; ret
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function %atomic_rmw_or_i64(i64, i64) {
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block0(v0: i64, v1: i64):
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v2 = atomic_rmw.i64 or v0, v1
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return
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}
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; VCode:
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; block0:
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; ldsetal x1, x3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldsetal x1, x3, [x0]
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; ret
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function %atomic_rmw_or_i32(i64, i32) {
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block0(v0: i64, v1: i32):
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v2 = atomic_rmw.i32 or v0, v1
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return
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}
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; VCode:
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; block0:
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; ldsetal w1, w3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldsetal w1, w3, [x0]
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; ret
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function %atomic_rmw_or_i16(i64, i16) {
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block0(v0: i64, v1: i16):
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v2 = atomic_rmw.i16 or v0, v1
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return
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}
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; VCode:
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; block0:
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; ldsetalh w1, w3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldsetalh w1, w3, [x0]
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; ret
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function %atomic_rmw_or_i8(i64, i8) {
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block0(v0: i64, v1: i8):
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v2 = atomic_rmw.i8 or v0, v1
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return
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}
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; VCode:
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; block0:
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; ldsetalb w1, w3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldsetalb w1, w3, [x0]
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; ret
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function %atomic_rmw_xor_i64(i64, i64) {
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block0(v0: i64, v1: i64):
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v2 = atomic_rmw.i64 xor v0, v1
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return
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}
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; VCode:
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; block0:
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; ldeoral x1, x3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldeoral x1, x3, [x0]
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; ret
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function %atomic_rmw_xor_i32(i64, i32) {
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block0(v0: i64, v1: i32):
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v2 = atomic_rmw.i32 xor v0, v1
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return
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}
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; VCode:
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; block0:
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; ldeoral w1, w3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldeoral w1, w3, [x0]
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; ret
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function %atomic_rmw_xor_i16(i64, i16) {
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block0(v0: i64, v1: i16):
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v2 = atomic_rmw.i16 xor v0, v1
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return
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}
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; VCode:
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; block0:
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; ldeoralh w1, w3, [x0]
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ldeoralh w1, w3, [x0]
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; ret
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function %atomic_rmw_xor_i8(i64, i8) {
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block0(v0: i64, v1: i8):
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v2 = atomic_rmw.i8 xor v0, v1
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return
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}
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; VCode:
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; block0:
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; ldeoralb w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldeoralb w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_smax_i64(i64, i64) {
|
|
block0(v0: i64, v1: i64):
|
|
v2 = atomic_rmw.i64 smax v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldsmaxal x1, x3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldsmaxal x1, x3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_smax_i32(i64, i32) {
|
|
block0(v0: i64, v1: i32):
|
|
v2 = atomic_rmw.i32 smax v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldsmaxal w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldsmaxal w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_smax_i16(i64, i16) {
|
|
block0(v0: i64, v1: i16):
|
|
v2 = atomic_rmw.i16 smax v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldsmaxalh w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldsmaxalh w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_smax_i8(i64, i8) {
|
|
block0(v0: i64, v1: i8):
|
|
v2 = atomic_rmw.i8 smax v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldsmaxalb w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldsmaxalb w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_umax_i64(i64, i64) {
|
|
block0(v0: i64, v1: i64):
|
|
v2 = atomic_rmw.i64 umax v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldumaxal x1, x3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldumaxal x1, x3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_umax_i32(i64, i32) {
|
|
block0(v0: i64, v1: i32):
|
|
v2 = atomic_rmw.i32 umax v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldumaxal w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldumaxal w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_umax_i16(i64, i16) {
|
|
block0(v0: i64, v1: i16):
|
|
v2 = atomic_rmw.i16 umax v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldumaxalh w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldumaxalh w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_umax_i8(i64, i8) {
|
|
block0(v0: i64, v1: i8):
|
|
v2 = atomic_rmw.i8 umax v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldumaxalb w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldumaxalb w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_smin_i64(i64, i64) {
|
|
block0(v0: i64, v1: i64):
|
|
v2 = atomic_rmw.i64 smin v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldsminal x1, x3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldsminal x1, x3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_smin_i32(i64, i32) {
|
|
block0(v0: i64, v1: i32):
|
|
v2 = atomic_rmw.i32 smin v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldsminal w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldsminal w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_smin_i16(i64, i16) {
|
|
block0(v0: i64, v1: i16):
|
|
v2 = atomic_rmw.i16 smin v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldsminalh w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldsminalh w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_smin_i8(i64, i8) {
|
|
block0(v0: i64, v1: i8):
|
|
v2 = atomic_rmw.i8 smin v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; ldsminalb w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; ldsminalb w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_umin_i64(i64, i64) {
|
|
block0(v0: i64, v1: i64):
|
|
v2 = atomic_rmw.i64 umin v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; lduminal x1, x3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; lduminal x1, x3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_umin_i32(i64, i32) {
|
|
block0(v0: i64, v1: i32):
|
|
v2 = atomic_rmw.i32 umin v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; lduminal w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; lduminal w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_umin_i16(i64, i16) {
|
|
block0(v0: i64, v1: i16):
|
|
v2 = atomic_rmw.i16 umin v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; lduminalh w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; lduminalh w1, w3, [x0]
|
|
; ret
|
|
|
|
function %atomic_rmw_umin_i8(i64, i8) {
|
|
block0(v0: i64, v1: i8):
|
|
v2 = atomic_rmw.i8 umin v0, v1
|
|
return
|
|
}
|
|
|
|
; VCode:
|
|
; block0:
|
|
; lduminalb w1, w3, [x0]
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; lduminalb w1, w3, [x0]
|
|
; ret
|
|
|