426c49b8e3
This patch introduces basic aarch64 code generation by using `cranelift-codegen`'s backend. This commit *does not*: * Change the semantics of the code generation * Adds support for other Wasm instructions The most notable change in this patch is how addressing modes are handled at the MacroAssembler layer: instead of having a canonical address representation, this patch introduces the addressing mode as an associated type in the MacroAssembler trait. This approach has the advantage that gives each ISA enough flexiblity to describe the addressing modes and their constraints in isolation without having to worry on how a particular addressing mode is going to affect other ISAs. In the case of Aarch64 this becomes useful to describe indexed addressing modes (particularly from the stack pointer). This patch uses the concept of a shadow stack pointer (x28) as a workaround to Aarch64's stack pointer 16-byte alignment. This constraint is enforced by: * Introducing specialized addressing modes when using the real stack pointer; this enables auditing when the real stack pointer is used. As of this change, the real stack pointer is only used in the function's prologue and epilogue. * Asserting that the real stack pointer is not used as a base for addressing modes. * Ensuring that at any point during the code generation process where the stack pointer changes (e.g. when stack space is allocated / deallocated) the value of the real stack pointer is copied into the shadow stack pointer.
72 lines
1.9 KiB
Rust
72 lines
1.9 KiB
Rust
//! Disassembly utilities.
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use anyhow::{bail, Result};
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use capstone::prelude::*;
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use std::fmt::Write;
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use target_lexicon::Architecture;
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use winch_codegen::TargetIsa;
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/// Disassemble and print a machine code buffer.
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pub fn disasm(bytes: &[u8], isa: &dyn TargetIsa) -> Result<Vec<String>> {
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let dis = disassembler_for(isa)?;
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let insts = dis.disasm_all(bytes, 0x0).unwrap();
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let disassembled_lines = insts
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.iter()
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.map(|i| {
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let mut line = String::new();
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write!(&mut line, "{:4x}:\t ", i.address()).unwrap();
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let mut bytes_str = String::new();
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let mut len = 0;
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for b in i.bytes() {
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write!(&mut bytes_str, "{:02x}", b).unwrap();
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len += 1;
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}
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write!(&mut line, "{:21}\t", bytes_str).unwrap();
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if len > 8 {
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write!(&mut line, "\n\t\t\t\t").unwrap();
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}
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if let Some(s) = i.mnemonic() {
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write!(&mut line, "{}\t", s).unwrap();
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}
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if let Some(s) = i.op_str() {
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write!(&mut line, "{}", s).unwrap();
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}
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line
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})
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.collect();
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Ok(disassembled_lines)
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}
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fn disassembler_for(isa: &dyn TargetIsa) -> Result<Capstone> {
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let disasm = match isa.triple().architecture {
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Architecture::X86_64 => Capstone::new()
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.x86()
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.mode(arch::x86::ArchMode::Mode64)
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.build()
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.map_err(|e| anyhow::format_err!("{}", e))?,
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Architecture::Aarch64 { .. } => {
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let mut cs = Capstone::new()
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.arm64()
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.mode(arch::arm64::ArchMode::Arm)
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.build()
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.map_err(|e| anyhow::format_err!("{}", e))?;
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cs.set_skipdata(true)
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.map_err(|e| anyhow::format_err!("{}", e))?;
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cs
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}
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_ => bail!("Unsupported ISA"),
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};
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Ok(disasm)
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}
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