c65de1f1b1
This is a follow-up to comments in #5795 to remove some cruft in the x64 instruction model to ensure that the shape of an `Inst` reflects what's going to happen in regalloc and encoding. This accessor was used to handle `round*`, `pextr*`, and `pshufb` instructions. The `round*` ones had already moved to the appropriate `XmmUnary*` variant and `pshufb` was additionally moved over to that variant as well. The `pextr*` instructions got a new `Inst` variant and additionally had their constructors slightly modified to no longer require the type as input. The encoding for these instructions now automatically handles the various type-related operands through a new `SseOpcode::Pextrq` operand to represent 64-bit movements.
820 lines
14 KiB
Plaintext
820 lines
14 KiB
Plaintext
test compile precise-output
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set enable_simd
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target x86_64
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function %band_f32x4(f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4):
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v2 = band v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; andps %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; andps %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %band_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = band v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; andpd %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; andpd %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %band_i32x4(i32x4, i32x4) -> i32x4 {
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block0(v0: i32x4, v1: i32x4):
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v2 = band v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pand %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pand %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %bor_f32x4(f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4):
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v2 = bor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; orps %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; orps %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %bor_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = bor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; orpd %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; orpd %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %bor_i32x4(i32x4, i32x4) -> i32x4 {
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block0(v0: i32x4, v1: i32x4):
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v2 = bor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; por %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; por %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %bxor_f32x4(f32x4, f32x4) -> f32x4 {
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block0(v0: f32x4, v1: f32x4):
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v2 = bxor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; xorps %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; xorps %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %bxor_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = bxor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; xorpd %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; xorpd %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %bxor_i32x4(i32x4, i32x4) -> i32x4 {
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block0(v0: i32x4, v1: i32x4):
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v2 = bxor v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pxor %xmm0, %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pxor %xmm1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %vselect_i16x8(i16x8, i16x8, i16x8) -> i16x8 {
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block0(v0: i16x8, v1: i16x8, v2: i16x8):
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v3 = vselect v0, v1, v2
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return v3
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqa %xmm2, %xmm4
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; pblendvb %xmm4, %xmm1, %xmm4
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; movdqa %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqa %xmm2, %xmm4
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; pblendvb %xmm0, %xmm1, %xmm4
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; movdqa %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %vselect_f32x4(i32x4, f32x4, f32x4) -> f32x4 {
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block0(v0: i32x4, v1: f32x4, v2: f32x4):
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v3 = vselect v0, v1, v2
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return v3
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqa %xmm2, %xmm4
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; blendvps %xmm4, %xmm1, %xmm4
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; movdqa %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqa %xmm2, %xmm4
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; blendvps %xmm0, %xmm1, %xmm4
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; movdqa %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %vselect_f64x2(i64x2, f64x2, f64x2) -> f64x2 {
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block0(v0: i64x2, v1: f64x2, v2: f64x2):
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v3 = vselect v0, v1, v2
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return v3
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqa %xmm2, %xmm4
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; blendvpd %xmm4, %xmm1, %xmm4
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; movdqa %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqa %xmm2, %xmm4
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; blendvpd %xmm0, %xmm1, %xmm4
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; movdqa %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %ishl_i8x16(i32) -> i8x16 {
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block0(v0: i32):
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v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v2 = ishl v1, v0
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqu const(1), %xmm0
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; movq %rdi, %r10
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; andq %r10, $7, %r10
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; movd %r10d, %xmm5
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; psllw %xmm0, %xmm5, %xmm0
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; lea const(0), %rsi
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; shlq $4, %r10, %r10
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; movdqu 0(%rsi,%r10,1), %xmm13
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; pand %xmm0, %xmm13, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqu 0xb4(%rip), %xmm0
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; movq %rdi, %r10
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; andq $7, %r10
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; movd %r10d, %xmm5
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; psllw %xmm5, %xmm0
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; leaq 0x1d(%rip), %rsi
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; shlq $4, %r10
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; movdqu (%rsi, %r10), %xmm13
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; pand %xmm13, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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function %ishl_i8x16_imm(i8x16) -> i8x16 {
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block0(v0: i8x16):
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v1 = iconst.i32 124
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v2 = ishl v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; psllw %xmm0, $4, %xmm0
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; movdqu const(0), %xmm4
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; pand %xmm0, %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; psllw $4, %xmm0
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; movdqu 0xf(%rip), %xmm4
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; pand %xmm4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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function %ishl_i16x8_imm(i16x8) -> i16x8 {
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block0(v0: i16x8):
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v1 = iconst.i32 1
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v2 = ishl v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; psllw %xmm0, $1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; psllw $1, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %ishl_i32x4_imm(i32x4) -> i32x4 {
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block0(v0: i32x4):
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v1 = iconst.i32 100
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v2 = ishl v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pslld %xmm0, $4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pslld $4, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %ishl_i64x2_imm(i64x2) -> i64x2 {
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block0(v0: i64x2):
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v1 = iconst.i32 100
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v2 = ishl v0, v1
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; psllq %xmm0, $36, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; psllq $0x24, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %ushr_i8x16_imm() -> i8x16 {
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block0:
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v0 = iconst.i32 1
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v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v2 = ushr v1, v0
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return v2
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqu const(1), %xmm0
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; psrlw %xmm0, $1, %xmm0
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; movdqu const(0), %xmm3
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; pand %xmm0, %xmm3, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqu 0x34(%rip), %xmm0
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; psrlw $1, %xmm0
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; movdqu 0x17(%rip), %xmm3
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; pand %xmm3, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; addb %al, (%rax)
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; jg 0xb1
|
|
; jg 0xb3
|
|
; jg 0xb5
|
|
; jg 0xb7
|
|
; jg 0xb9
|
|
; jg 0xbb
|
|
; jg 0xbd
|
|
; jg 0xbf
|
|
; addb %al, (%rcx)
|
|
; addb (%rbx), %al
|
|
; addb $5, %al
|
|
|
|
function %ushr_i16x8_imm(i16x8) -> i16x8 {
|
|
block0(v0: i16x8):
|
|
v1 = iconst.i32 1
|
|
v2 = ushr v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; psrlw %xmm0, $1, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; psrlw $1, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %ushr_i32x4_imm(i32x4) -> i32x4 {
|
|
block0(v0: i32x4):
|
|
v1 = iconst.i32 100
|
|
v2 = ushr v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; psrld %xmm0, $4, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; psrld $4, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %ushr_i64x2_imm(i64x2) -> i64x2 {
|
|
block0(v0: i64x2):
|
|
v1 = iconst.i32 100
|
|
v2 = ushr v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; psrlq %xmm0, $36, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; psrlq $0x24, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %sshr_i8x16(i32) -> i8x16 {
|
|
block0(v0: i32):
|
|
v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
|
|
v2 = sshr v1, v0
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; movdqu const(0), %xmm8
|
|
; movq %rdi, %r9
|
|
; andq %r9, $7, %r9
|
|
; movdqa %xmm8, %xmm0
|
|
; punpcklbw %xmm0, %xmm8, %xmm0
|
|
; punpckhbw %xmm8, %xmm8, %xmm8
|
|
; addl %r9d, $8, %r9d
|
|
; movd %r9d, %xmm11
|
|
; psraw %xmm0, %xmm11, %xmm0
|
|
; psraw %xmm8, %xmm11, %xmm8
|
|
; packsswb %xmm0, %xmm8, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; movdqu 0x33(%rip), %xmm8
|
|
; movq %rdi, %r9
|
|
; andq $7, %r9
|
|
; movdqa %xmm8, %xmm0
|
|
; punpcklbw %xmm8, %xmm0
|
|
; punpckhbw %xmm8, %xmm8
|
|
; addl $8, %r9d
|
|
; movd %r9d, %xmm11
|
|
; psraw %xmm11, %xmm0
|
|
; psraw %xmm11, %xmm8
|
|
; packsswb %xmm8, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
; addb %al, (%rcx)
|
|
; addb (%rbx), %al
|
|
; addb $5, %al
|
|
|
|
function %sshr_i8x16_imm(i8x16, i32) -> i8x16 {
|
|
block0(v0: i8x16, v1: i32):
|
|
v2 = sshr_imm v0, 3
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; movdqa %xmm0, %xmm7
|
|
; punpcklbw %xmm7, %xmm0, %xmm7
|
|
; movdqa %xmm7, %xmm8
|
|
; movdqa %xmm0, %xmm7
|
|
; punpckhbw %xmm7, %xmm0, %xmm7
|
|
; movdqa %xmm8, %xmm0
|
|
; psraw %xmm0, $11, %xmm0
|
|
; psraw %xmm7, $11, %xmm7
|
|
; packsswb %xmm0, %xmm7, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; movdqa %xmm0, %xmm7
|
|
; punpcklbw %xmm0, %xmm7
|
|
; movdqa %xmm7, %xmm8
|
|
; movdqa %xmm0, %xmm7
|
|
; punpckhbw %xmm0, %xmm7
|
|
; movdqa %xmm8, %xmm0
|
|
; psraw $0xb, %xmm0
|
|
; psraw $0xb, %xmm7
|
|
; packsswb %xmm7, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %sshr_i16x8_imm(i16x8) -> i16x8 {
|
|
block0(v0: i16x8):
|
|
v1 = iconst.i32 1
|
|
v2 = sshr v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; psraw %xmm0, $1, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; psraw $1, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %sshr_i32x4_imm(i32x4) -> i32x4 {
|
|
block0(v0: i32x4):
|
|
v1 = iconst.i32 100
|
|
v2 = sshr v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; psrad %xmm0, $4, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; psrad $4, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %sshr_i64x2_imm(i64x2) -> i64x2 {
|
|
block0(v0: i64x2):
|
|
v1 = iconst.i32 100
|
|
v2 = sshr v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; pextrq $0, %xmm0, %rdx
|
|
; pextrq $1, %xmm0, %r9
|
|
; sarq $36, %rdx, %rdx
|
|
; sarq $36, %r9, %r9
|
|
; uninit %xmm0
|
|
; pinsrd.w $0, %xmm0, %rdx, %xmm0
|
|
; pinsrd.w $1, %xmm0, %r9, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; pextrq $0, %xmm0, %rdx
|
|
; pextrq $1, %xmm0, %r9
|
|
; sarq $0x24, %rdx
|
|
; sarq $0x24, %r9
|
|
; pinsrq $0, %rdx, %xmm0
|
|
; pinsrq $1, %r9, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|
|
function %sshr_i64x2(i64x2, i32) -> i64x2 {
|
|
block0(v0: i64x2, v1: i32):
|
|
v2 = sshr v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode:
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block0:
|
|
; pextrq $0, %xmm0, %r8
|
|
; pextrq $1, %xmm0, %r10
|
|
; movq %rdi, %rcx
|
|
; sarq %cl, %r8, %r8
|
|
; sarq %cl, %r10, %r10
|
|
; uninit %xmm0
|
|
; pinsrd.w $0, %xmm0, %r8, %xmm0
|
|
; pinsrd.w $1, %xmm0, %r10, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; ret
|
|
;
|
|
; Disassembled:
|
|
; block0: ; offset 0x0
|
|
; pushq %rbp
|
|
; movq %rsp, %rbp
|
|
; block1: ; offset 0x4
|
|
; pextrq $0, %xmm0, %r8
|
|
; pextrq $1, %xmm0, %r10
|
|
; movq %rdi, %rcx
|
|
; sarq %cl, %r8
|
|
; sarq %cl, %r10
|
|
; pinsrq $0, %r8, %xmm0
|
|
; pinsrq $1, %r10, %xmm0
|
|
; movq %rbp, %rsp
|
|
; popq %rbp
|
|
; retq
|
|
|