dd40bf075a
This enables more runtests to be executed on s390x. Doing so
uncovered a two back-end bugs, which are fixed as well:
- The result of cls was always off by one.
- The result of popcnt.i16 has uninitialized high bits.
In addition, I found a bug in the load-op-store.clif test case:
v3 = heap_addr.i64 heap0, v1, 4
v4 = iconst.i64 42
store.i32 v4, v3
This was clearly intended to perform a 32-bit store, but
actually performs a 64-bit store (it seems the type annotation
of the store opcode is ignored, and the type of the operand
is used instead). That bug did not show any noticable symptoms
on little-endian architectures, but broke on big-endian.
97 lines
2.7 KiB
Plaintext
97 lines
2.7 KiB
Plaintext
test run
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target x86_64
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target s390x
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target aarch64
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function %load_op_store_iadd_i64(i64 vmctx, i64, i64) -> i64 {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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heap0 = static gv1, min 0x1000, bound 0x1_0000_0000, offset_guard 0, index_type i64
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block0(v0: i64, v1: i64, v2: i64):
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v3 = heap_addr.i64 heap0, v1, 8
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v4 = iconst.i64 42
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store.i64 v4, v3
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v5 = load.i64 v3
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v6 = iadd.i64 v5, v2
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store.i64 v6, v3
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v7 = load.i64 v3
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return v7
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}
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; heap: static, size=0x1000, ptr=vmctx+0, bound=vmctx+8
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; run: %static_heap_i64_load_store(0, 1) == 43
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; run: %static_heap_i64_load_store(0, -1) == 41
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function %load_op_store_iadd_i32(i64 vmctx, i64, i32) -> i32 {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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heap0 = static gv1, min 0x1000, bound 0x1_0000_0000, offset_guard 0, index_type i64
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block0(v0: i64, v1: i64, v2: i32):
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v3 = heap_addr.i64 heap0, v1, 4
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v4 = iconst.i32 42
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store.i32 v4, v3
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v5 = load.i32 v3
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v6 = iadd.i32 v5, v2
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store.i32 v6, v3
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v7 = load.i32 v3
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return v7
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}
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; heap: static, size=0x1000, ptr=vmctx+0, bound=vmctx+8
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; run: %static_heap_i64_load_store(0, 1) == 43
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; run: %static_heap_i64_load_store(0, -1) == 41
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function %load_op_store_iadd_i8(i64 vmctx, i64, i8) -> i8 {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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heap0 = static gv1, min 0x1000, bound 0x1_0000_0000, offset_guard 0, index_type i64
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block0(v0: i64, v1: i64, v2: i8):
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v3 = heap_addr.i64 heap0, v1, 4
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v4 = iconst.i8 42
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store.i8 v4, v3
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v5 = load.i8 v3
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v6 = iadd.i8 v5, v2
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store.i8 v6, v3
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v7 = load.i8 v3
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return v7
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}
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; heap: static, size=0x1000, ptr=vmctx+0, bound=vmctx+8
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; run: %static_heap_i64_load_store(0, 1) == 43
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; run: %static_heap_i64_load_store(0, -1) == 41
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function %load_op_store_iadd_isub_iand_ior_ixor_i64(i64 vmctx, i64, i64) -> i64 {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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heap0 = static gv1, min 0x1000, bound 0x1_0000_0000, offset_guard 0, index_type i64
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block0(v0: i64, v1: i64, v2: i64):
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v3 = heap_addr.i64 heap0, v1, 8
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store.i64 v2, v3
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v4 = load.i64 v3
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v5 = iconst.i64 1
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v6 = iadd.i64 v5, v4
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store.i64 v6, v3
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v7 = load.i64 v3
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v8 = iconst.i64 2
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v9 = load.i64 v3
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v10 = isub.i64 v9, v8
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store.i64 v10, v3
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v11 = load.i64 v3
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v12 = iconst.i64 0xf
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v13 = band.i64 v12, v11
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store.i64 v13, v3
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v14 = iconst.i64 0x10
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v15 = load.i64 v3
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v16 = bor.i64 v15, v14
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store.i64 v16, v3
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v17 = load.i64 v3
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v18 = iconst.i64 0xff
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v19 = bxor.i64 v17, v18
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store.i64 v19, v3
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v20 = load.i64 v3
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return v20
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}
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; heap: static, size=0x1000, ptr=vmctx+0, bound=vmctx+8
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; run: %static_heap_i64_load_store(0, 0x1234) == 236
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