c5b15c2396
Add a calling-convention setting to the `Flags` used as part of the `TargetIsa`. This allows Cretonne code that generates calls to use the correct convention, such as when emitting libcalls during legalization or when the wasm frontend is decoding functions. This setting can be overridden per-function. This also adds "fast", "cold", and "fastcall" conventions, with "fast" as the new default. Note that "fast" and "cold" are not intended to be ABI-compatible across Cretonne versions. This will also ensure Windows users will get an `unimplemented!` rather than silent calling-convention mismatches, which reflects the fact that Windows calling conventions are not yet implemented. This also renames SpiderWASM, which isn't camel-case, to Baldrdash, which is, and which is also a more relevant name.
141 lines
3.1 KiB
Plaintext
141 lines
3.1 KiB
Plaintext
test regalloc
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set is_64bit
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isa x86 haswell
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function u0:9(i64 [%rdi], f32 [%xmm0], f64 [%xmm1], i32 [%rsi], i32 [%rdx], i64 vmctx [%r14]) -> i64 [%rax] baldrdash {
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ebb0(v0: i64, v1: f32, v2: f64, v3: i32, v4: i32, v5: i64):
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v32 = iconst.i32 0
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v6 = bitcast.f32 v32
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v7 = iconst.i64 0
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v33 = iconst.i64 0
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v8 = bitcast.f64 v33
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v34 = iconst.i32 0xbe99_999a
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v9 = bitcast.f32 v34
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v10 = iconst.i32 40
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v11 = iconst.i32 -7
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v35 = iconst.i32 0x40b0_0000
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v12 = bitcast.f32 v35
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v13 = iconst.i64 6
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v36 = iconst.i64 0x4020_0000_0000_0000
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v14 = bitcast.f64 v36
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v44 = iconst.i64 0
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v37 = icmp slt v0, v44
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brnz v37, ebb2
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v38 = fcvt_from_sint.f64 v0
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jump ebb3(v38)
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ebb2:
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v45 = iconst.i32 1
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v39 = ushr.i64 v0, v45
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v40 = band_imm.i64 v0, 1
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v41 = bor v39, v40
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v42 = fcvt_from_sint.f64 v41
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v43 = fadd v42, v42
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jump ebb3(v43)
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ebb3(v15: f64):
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v16 = fpromote.f64 v9
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v46 = uextend.i64 v10
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v17 = fcvt_from_sint.f64 v46
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v18 = fcvt_from_sint.f64 v11
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v19 = fpromote.f64 v12
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v54 = iconst.i64 0
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v47 = icmp.i64 slt v13, v54
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brnz v47, ebb4
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v48 = fcvt_from_sint.f64 v13
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jump ebb5(v48)
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ebb4:
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v55 = iconst.i32 1
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v49 = ushr.i64 v13, v55
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v50 = band_imm.i64 v13, 1
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v51 = bor v49, v50
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v52 = fcvt_from_sint.f64 v51
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v53 = fadd v52, v52
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jump ebb5(v53)
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ebb5(v20: f64):
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v63 = iconst.i64 0
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v56 = icmp.i64 slt v7, v63
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brnz v56, ebb6
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v57 = fcvt_from_sint.f64 v7
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jump ebb7(v57)
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ebb6:
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v64 = iconst.i32 1
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v58 = ushr.i64 v7, v64
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v59 = band_imm.i64 v7, 1
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v60 = bor v58, v59
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v61 = fcvt_from_sint.f64 v60
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v62 = fadd v61, v61
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jump ebb7(v62)
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ebb7(v21: f64):
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v22 = fadd v21, v14
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v23 = fadd.f64 v20, v22
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v24 = fadd.f64 v19, v23
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v25 = fadd.f64 v18, v24
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v26 = fadd.f64 v17, v25
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v27 = fadd.f64 v2, v26
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v28 = fadd.f64 v16, v27
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v29 = fadd.f64 v15, v28
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v30 = x86_cvtt2si.i64 v29
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v69 = iconst.i64 0x8000_0000_0000_0000
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v65 = icmp ne v30, v69
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brnz v65, ebb8
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v66 = fcmp uno v29, v29
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brz v66, ebb9
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trap bad_toint
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ebb9:
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v70 = iconst.i64 0xc3e0_0000_0000_0000
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v67 = bitcast.f64 v70
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v68 = fcmp gt v67, v29
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brz v68, ebb10
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trap int_ovf
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ebb10:
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jump ebb8
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ebb8:
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jump ebb1(v30)
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ebb1(v31: i64):
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return v31
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}
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function u0:26(i64 vmctx [%r14]) -> i64 [%rax] baldrdash {
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gv0 = vmctx+48
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sig0 = (i32 [%rdi], i64 [%rsi], i64 vmctx [%r14], i64 sigid [%rbx]) -> i64 [%rax] baldrdash
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ebb0(v0: i64):
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v1 = iconst.i32 32
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v2 = iconst.i64 64
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v3 = iconst.i32 9
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v4 = iconst.i64 1063
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v5 = iadd_imm v0, 48
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v6 = load.i32 v5
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v7 = icmp uge v3, v6
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; If we're unlucky, there are no ABCD registers available for v7 at this branch.
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brz v7, ebb2
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trap oob
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ebb2:
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v8 = load.i64 v5+8
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v9 = uextend.i64 v3
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v16 = iconst.i64 16
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v10 = imul v9, v16
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v11 = iadd v8, v10
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v12 = load.i64 v11
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brnz v12, ebb3
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trap icall_null
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ebb3:
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v13 = load.i64 v11+8
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v14 = call_indirect.i64 sig0, v12(v1, v2, v13, v4)
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jump ebb1(v14)
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ebb1(v15: i64):
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return v15
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}
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