335 lines
10 KiB
Rust
335 lines
10 KiB
Rust
//! AArch64 ISA definitions: registers.
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use crate::ir::types::*;
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use crate::isa::aarch64::inst::InstSize;
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use crate::machinst::*;
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use crate::settings;
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use regalloc::{RealRegUniverse, Reg, RegClass, RegClassInfo, Writable, NUM_REG_CLASSES};
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use std::string::{String, ToString};
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//=============================================================================
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// Registers, the Universe thereof, and printing
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/// The pinned register on this architecture.
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/// It must be the same as Spidermonkey's HeapReg, as found in this file.
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/// https://searchfox.org/mozilla-central/source/js/src/jit/arm64/Assembler-arm64.h#103
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pub const PINNED_REG: u8 = 21;
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#[rustfmt::skip]
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const XREG_INDICES: [u8; 31] = [
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// X0 - X7
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32, 33, 34, 35, 36, 37, 38, 39,
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// X8 - X15
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40, 41, 42, 43, 44, 45, 46, 47,
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// X16, X17
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58, 59,
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// X18
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60,
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// X19, X20
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48, 49,
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// X21, put aside because it's the pinned register.
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57,
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// X22 - X28
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50, 51, 52, 53, 54, 55, 56,
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// X29 (FP)
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61,
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// X30 (LR)
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62,
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];
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const ZERO_REG_INDEX: u8 = 63;
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const SP_REG_INDEX: u8 = 64;
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/// Get a reference to an X-register (integer register).
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pub fn xreg(num: u8) -> Reg {
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assert!(num < 31);
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Reg::new_real(
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RegClass::I64,
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/* enc = */ num,
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/* index = */ XREG_INDICES[num as usize],
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)
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}
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/// Get a writable reference to an X-register.
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pub fn writable_xreg(num: u8) -> Writable<Reg> {
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Writable::from_reg(xreg(num))
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}
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/// Get a reference to a V-register (vector/FP register).
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pub fn vreg(num: u8) -> Reg {
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assert!(num < 32);
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Reg::new_real(RegClass::V128, /* enc = */ num, /* index = */ num)
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}
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/// Get a writable reference to a V-register.
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pub fn writable_vreg(num: u8) -> Writable<Reg> {
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Writable::from_reg(vreg(num))
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}
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/// Get a reference to the zero-register.
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pub fn zero_reg() -> Reg {
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// This should be the same as what xreg(31) returns, except that
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// we use the special index into the register index space.
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Reg::new_real(
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RegClass::I64,
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/* enc = */ 31,
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/* index = */ ZERO_REG_INDEX,
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)
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}
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/// Get a writable reference to the zero-register (this discards a result).
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pub fn writable_zero_reg() -> Writable<Reg> {
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Writable::from_reg(zero_reg())
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}
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/// Get a reference to the stack-pointer register.
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pub fn stack_reg() -> Reg {
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// XSP (stack) and XZR (zero) are logically different registers which have
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// the same hardware encoding, and whose meaning, in real aarch64
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// instructions, is context-dependent. For convenience of
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// universe-construction and for correct printing, we make them be two
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// different real registers.
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Reg::new_real(
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RegClass::I64,
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/* enc = */ 31,
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/* index = */ SP_REG_INDEX,
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)
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}
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/// Get a writable reference to the stack-pointer register.
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pub fn writable_stack_reg() -> Writable<Reg> {
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Writable::from_reg(stack_reg())
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}
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/// Get a reference to the link register (x30).
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pub fn link_reg() -> Reg {
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xreg(30)
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}
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/// Get a writable reference to the link register.
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pub fn writable_link_reg() -> Writable<Reg> {
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Writable::from_reg(link_reg())
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}
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/// Get a reference to the frame pointer (x29).
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pub fn fp_reg() -> Reg {
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xreg(29)
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}
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/// Get a writable reference to the frame pointer.
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pub fn writable_fp_reg() -> Writable<Reg> {
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Writable::from_reg(fp_reg())
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}
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/// Get a reference to the first temporary, sometimes "spill temporary", register. This register is
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/// used to compute the address of a spill slot when a direct offset addressing mode from FP is not
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/// sufficient (+/- 2^11 words). We exclude this register from regalloc and reserve it for this
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/// purpose for simplicity; otherwise we need a multi-stage analysis where we first determine how
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/// many spill slots we have, then perhaps remove the reg from the pool and recompute regalloc.
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///
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/// We use x16 for this (aka IP0 in the AArch64 ABI) because it's a scratch register but is
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/// slightly special (used for linker veneers). We're free to use it as long as we don't expect it
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/// to live through call instructions.
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pub fn spilltmp_reg() -> Reg {
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xreg(16)
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}
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/// Get a writable reference to the spilltmp reg.
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pub fn writable_spilltmp_reg() -> Writable<Reg> {
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Writable::from_reg(spilltmp_reg())
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}
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/// Get a reference to the second temp register. We need this in some edge cases
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/// where we need both the spilltmp and another temporary.
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///
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/// We use x17 (aka IP1), the other "interprocedural"/linker-veneer scratch reg that is
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/// free to use otherwise.
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pub fn tmp2_reg() -> Reg {
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xreg(17)
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}
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/// Get a writable reference to the tmp2 reg.
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pub fn writable_tmp2_reg() -> Writable<Reg> {
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Writable::from_reg(tmp2_reg())
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}
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/// Create the register universe for AArch64.
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pub fn create_reg_universe(flags: &settings::Flags) -> RealRegUniverse {
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let mut regs = vec![];
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let mut allocable_by_class = [None; NUM_REG_CLASSES];
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// Numbering Scheme: we put V-regs first, then X-regs. The X-regs exclude several registers:
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// x18 (globally reserved for platform-specific purposes), x29 (frame pointer), x30 (link
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// register), x31 (stack pointer or zero register, depending on context).
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let v_reg_base = 0u8; // in contiguous real-register index space
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let v_reg_count = 32;
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for i in 0u8..v_reg_count {
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let reg = Reg::new_real(
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RegClass::V128,
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/* enc = */ i,
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/* index = */ v_reg_base + i,
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)
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.to_real_reg();
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let name = format!("v{}", i);
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regs.push((reg, name));
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}
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let v_reg_last = v_reg_base + v_reg_count - 1;
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// Add the X registers. N.B.: the order here must match the order implied
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// by XREG_INDICES, ZERO_REG_INDEX, and SP_REG_INDEX above.
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let x_reg_base = 32u8; // in contiguous real-register index space
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let mut x_reg_count = 0;
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let uses_pinned_reg = flags.enable_pinned_reg();
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for i in 0u8..32u8 {
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// See above for excluded registers.
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if i == 16 || i == 17 || i == 18 || i == 29 || i == 30 || i == 31 || i == PINNED_REG {
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continue;
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}
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let reg = Reg::new_real(
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RegClass::I64,
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/* enc = */ i,
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/* index = */ x_reg_base + x_reg_count,
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)
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.to_real_reg();
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let name = format!("x{}", i);
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regs.push((reg, name));
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x_reg_count += 1;
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}
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let x_reg_last = x_reg_base + x_reg_count - 1;
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allocable_by_class[RegClass::I64.rc_to_usize()] = Some(RegClassInfo {
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first: x_reg_base as usize,
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last: x_reg_last as usize,
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suggested_scratch: Some(XREG_INDICES[19] as usize),
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});
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allocable_by_class[RegClass::V128.rc_to_usize()] = Some(RegClassInfo {
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first: v_reg_base as usize,
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last: v_reg_last as usize,
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suggested_scratch: Some(/* V31: */ 31),
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});
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// Other regs, not available to the allocator.
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let allocable = if uses_pinned_reg {
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// The pinned register is not allocatable in this case, so record the length before adding
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// it.
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let len = regs.len();
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regs.push((xreg(PINNED_REG).to_real_reg(), "x21/pinned_reg".to_string()));
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len
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} else {
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regs.push((xreg(PINNED_REG).to_real_reg(), "x21".to_string()));
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regs.len()
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};
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regs.push((xreg(16).to_real_reg(), "x16".to_string()));
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regs.push((xreg(17).to_real_reg(), "x17".to_string()));
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regs.push((xreg(18).to_real_reg(), "x18".to_string()));
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regs.push((fp_reg().to_real_reg(), "fp".to_string()));
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regs.push((link_reg().to_real_reg(), "lr".to_string()));
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regs.push((zero_reg().to_real_reg(), "xzr".to_string()));
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regs.push((stack_reg().to_real_reg(), "sp".to_string()));
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// FIXME JRS 2020Feb06: unfortunately this pushes the number of real regs
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// to 65, which is potentially inconvenient from a compiler performance
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// standpoint. We could possibly drop back to 64 by "losing" a vector
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// register in future.
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// Assert sanity: the indices in the register structs must match their
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// actual indices in the array.
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for (i, reg) in regs.iter().enumerate() {
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assert_eq!(i, reg.0.get_index());
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}
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RealRegUniverse {
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regs,
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allocable,
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allocable_by_class,
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}
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}
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/// If `ireg` denotes an I64-classed reg, make a best-effort attempt to show
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/// its name at the 32-bit size.
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pub fn show_ireg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: InstSize) -> String {
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let mut s = reg.show_rru(mb_rru);
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if reg.get_class() != RegClass::I64 || !size.is32() {
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// We can't do any better.
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return s;
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}
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if reg.is_real() {
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// Change (eg) "x42" into "w42" as appropriate
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if reg.get_class() == RegClass::I64 && size.is32() && s.starts_with("x") {
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s = "w".to_string() + &s[1..];
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}
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} else {
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// Add a "w" suffix to RegClass::I64 vregs used in a 32-bit role
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if reg.get_class() == RegClass::I64 && size.is32() {
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s.push('w');
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}
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}
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s
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}
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/// Show a vector register.
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pub fn show_freg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: InstSize) -> String {
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let mut s = reg.show_rru(mb_rru);
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if reg.get_class() != RegClass::V128 {
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return s;
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}
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let prefix = match size {
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InstSize::Size32 => "s",
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InstSize::Size64 => "d",
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InstSize::Size128 => "q",
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};
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s.replace_range(0..1, prefix);
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s
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}
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/// Show a vector register used in a scalar context.
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pub fn show_vreg_scalar(reg: Reg, mb_rru: Option<&RealRegUniverse>) -> String {
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let mut s = reg.show_rru(mb_rru);
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if reg.get_class() != RegClass::V128 {
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// We can't do any better.
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return s;
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}
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if reg.is_real() {
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// Change (eg) "v0" into "d0".
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if reg.get_class() == RegClass::V128 && s.starts_with("v") {
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s.replace_range(0..1, "d");
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}
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} else {
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// Add a "d" suffix to RegClass::V128 vregs.
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if reg.get_class() == RegClass::V128 {
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s.push('d');
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}
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}
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s
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}
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/// Show a vector register.
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pub fn show_vreg_vector(reg: Reg, mb_rru: Option<&RealRegUniverse>, ty: Type) -> String {
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assert_eq!(RegClass::V128, reg.get_class());
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let mut s = reg.show_rru(mb_rru);
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match ty {
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I8X16 => s.push_str(".16b"),
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I16X8 => s.push_str(".8h"),
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I32X4 => s.push_str(".4s"),
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F32X2 => s.push_str(".2s"),
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I8X8 => s.push_str(".8b"),
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I16X4 => s.push_str(".4h"),
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I32X2 => s.push_str(".2s"),
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I64X2 => s.push_str(".2d"),
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_ => unimplemented!(),
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}
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s
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}
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