bb8ae9a4fb
This gives the target ISA a chance to reserve registers like the stack pointer or hard-wired 0 registers like %x0 on RISC-V.
14 lines
251 B
Plaintext
14 lines
251 B
Plaintext
test regalloc
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; We can add more ISAs once they have defined encodings.
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isa riscv
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function add(i32, i32) {
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ebb0(v1: i32, v2: i32):
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v3 = iadd v1, v2
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; TODO: This shouldn't clobber the link register.
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; check: [R#0c,%x1]
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; sameln: iadd
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return
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}
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