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bb2dd5b68b367df3305a98914eb9baeafa80bc03
wasmtime/cranelift/filetests/filetests/isa/x64
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Andrew Brown bb2dd5b68b [machinst x64]: implement load*_zero for x64
2021-01-08 16:21:57 -08:00
..
amode-opt.clif
x64 regalloc register order: put caller-saves (volatiles) first.
2020-12-06 22:37:43 -08:00
b1.clif
x64: handle tests of b1 values correctly (only LSB is defined).
2021-01-05 14:45:46 -08:00
basic.clif
machinst x64: enable clif testing
2020-09-25 11:12:21 +02:00
branches.clif
Add support for brff/brif and icmp_sp to new x64 backend to support Lucet.
2020-11-11 13:43:39 -08:00
heap.clif
x64 regalloc register order: put caller-saves (volatiles) first.
2020-12-06 22:37:43 -08:00
load-op.clif
x64 regalloc register order: put caller-saves (volatiles) first.
2020-12-06 22:37:43 -08:00
move-elision.clif
[machinst x64]: demonstrate that packed register moves are elided
2020-09-29 08:48:37 -07:00
popcnt.clif
x64 lowering fix: i32.popcnt should not merge load and make it 64-bit.
2020-12-08 12:24:34 -08:00
probestack.clif
Two Lucet-related fixes to stack overflow handling.
2020-12-07 16:08:53 -08:00
run-const.clif
machinst x64: enable clif testing
2020-09-25 11:12:21 +02:00
simd-arithmetic-run.clif
[machinst x64]: enable packed saturated arithmetic
2020-10-08 08:46:20 -07:00
simd-bitwise-compile.clif
x64 regalloc register order: put caller-saves (volatiles) first.
2020-12-06 22:37:43 -08:00
simd-bitwise-run.clif
[machinst x64]: implement packed shifts
2020-11-12 14:21:45 -08:00
simd-comparison-legalize.clif
[machinst x64]: port CLIF tests related to comparison and lane operations
2020-10-02 08:29:31 -07:00
simd-comparison-run.clif
[machinst x64]: port CLIF tests related to comparison and lane operations
2020-10-02 08:29:31 -07:00
simd-conversion-run.clif
Add filetests for fcvt_from_sint.f32x4
2020-10-28 13:02:50 -07:00
simd-lane-access-compile.clif
[machinst x64]: implement load*_zero for x64
2021-01-08 16:21:57 -08:00
simd-lane-access-run.clif
[machinst x64]: port CLIF tests related to comparison and lane operations
2020-10-02 08:29:31 -07:00
simd-logical-compile.clif
x64 regalloc register order: put caller-saves (volatiles) first.
2020-12-06 22:37:43 -08:00
simd-logical-run.clif
[machinst x64]: port more CLIF filetests
2020-10-09 10:04:50 -07:00
uextend-elision.clif
machinst x64: avoid emitting movzx when the input is an ALU 32-bits operation;
2020-10-09 18:49:27 +02:00