Jakob Stoklund Olesen b6c2d4588f Add a LiveRange data structure. ...

We will track live ranges separately for each SSA value, rather than per
virtual register like LLVM does.

This is the basis for a register allocator, so place it in a new
regalloc module.

2017-01-06 17:16:25 -08:00

..

ir

Add a LiveRange data structure.

2017-01-06 17:16:25 -08:00

isa

Fill in boilerplate for Intel and ARM targets.

2016-11-23 10:42:07 -08:00

regalloc

Add a LiveRange data structure.

2017-01-06 17:16:25 -08:00

cfg.rs

Require documentation on cretonne public items.

2016-10-26 19:10:06 -07:00

constant_hash.rs

File stale path references.

2016-10-24 13:27:10 -07:00

dominator_tree.rs

Require documentation on cretonne public items.

2016-10-26 19:10:06 -07:00

entity_map.rs

Move library crates under 'lib/'.

2016-10-17 14:44:43 -07:00

legalizer.rs

Revisit expanded instructions for legalization.

2016-11-04 09:44:11 -07:00

lib.rs

Add a LiveRange data structure.

2017-01-06 17:16:25 -08:00

predicates.rs

File stale path references.

2016-10-24 13:27:10 -07:00

ref_slice.rs

Add a ref_slice module.

2016-11-04 12:32:09 -07:00

settings.rs

Fill in boilerplate for Intel and ARM targets.

2016-11-23 10:42:07 -08:00

verifier.rs

remove old is_terminating function

2016-12-07 10:16:01 -10:00

write.rs

Write out value aliases when writing instructions.

2016-11-04 15:28:51 -07:00