65e6de2344
Since the Wasm specification contains narrowing instructions (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing) that lower to PACKSS*, the x86-specific instruction is not necessary in the CLIF IR.
112 lines
2.7 KiB
Plaintext
112 lines
2.7 KiB
Plaintext
test legalizer
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set enable_simd
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target x86_64 skylake
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function %ushr_i8x16() -> i8x16 {
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block0:
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v0 = iconst.i32 1
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v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v2 = ushr v1, v0
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; check: v3 = bitcast.i64x2 v0
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; nextln: v4 = raw_bitcast.i16x8 v1
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; nextln: v5 = x86_psrl v4, v3
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; nextln: v6 = raw_bitcast.i8x16 v5
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; nextln: v7 = const_addr.i64 const1
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; nextln: v8 = ishl_imm v0, 4
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; nextln: v9 = load_complex.i8x16 v7+v8
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; nextln: v2 = band v6, v9
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return v2
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}
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function %sshr_i8x16() -> i8x16 {
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block0:
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v0 = iconst.i32 1
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v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v2 = sshr v1, v0
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; check: v3 = iadd_imm v0, 8
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; nextln: v4 = bitcast.i64x2 v3
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; nextln: v5 = x86_punpckl v1, v1
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; nextln: v6 = raw_bitcast.i16x8 v5
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; nextln: v7 = x86_psra v6, v4
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; nextln: v8 = x86_punpckh v1, v1
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; nextln: v9 = raw_bitcast.i16x8 v8
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; nextln: v10 = x86_psra v9, v4
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; nextln: v2 = snarrow v7, v10
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return v2
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}
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function %ishl_i8x16() -> i8x16 {
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block0:
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v0 = iconst.i32 1
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v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
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v2 = ishl v1, v0
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; check: v3 = bitcast.i64x2 v0
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; nextln: v4 = raw_bitcast.i16x8 v1
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; nextln: v5 = x86_psll v4, v3
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; nextln: v6 = raw_bitcast.i8x16 v5
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; nextln: v7 = const_addr.i64 const1
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; nextln: v8 = ishl_imm v0, 4
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; nextln: v9 = load_complex.i8x16 v7+v8
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; nextln: v2 = band v6, v9
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return v2
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}
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function %ishl_i32x4() -> i32x4 {
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block0:
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v0 = iconst.i32 1
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v1 = vconst.i32x4 [1 2 4 8]
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v2 = ishl v1, v0
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; check: v3 = bitcast.i64x2 v0
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; nextln: v2 = x86_psll v1, v3
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return v2
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}
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function %ushr_i64x2() -> i64x2 {
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block0:
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v0 = iconst.i32 1
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v1 = vconst.i64x2 [1 2]
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v2 = ushr v1, v0
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; check: v3 = bitcast.i64x2 v0
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; nextln: v2 = x86_psrl v1, v3
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return v2
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}
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function %sshr_i16x8() -> i16x8 {
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block0:
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v0 = iconst.i32 1
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v1 = vconst.i16x8 [1 2 4 8 16 32 64 128]
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v2 = sshr v1, v0
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; check: v3 = bitcast.i64x2 v0
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; nextln: v2 = x86_psra v1, v3
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return v2
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}
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function %sshr_i64x2() -> i64x2 {
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block0:
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v0 = iconst.i32 1
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v1 = vconst.i64x2 [1 2]
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v2 = sshr v1, v0
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; check: v3 = x86_pextr v1, 0
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; nextln: v4 = sshr v3, v0
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; nextln: v5 = x86_pinsr v1, v4, 0
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; nextln: v6 = x86_pextr v1, 1
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; nextln: v7 = sshr v6, v0
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; nextln: v2 = x86_pinsr v5, v7, 1
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return v2
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}
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function %bitselect_i16x8() -> i16x8 {
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block0:
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v0 = vconst.i16x8 [0 0 0 0 0 0 0 0]
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v1 = vconst.i16x8 [0 0 0 0 0 0 0 0]
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v2 = vconst.i16x8 [0 0 0 0 0 0 0 0]
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v3 = bitselect v0, v1, v2
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; check: v4 = band v1, v0
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; nextln: v5 = band_not v2, v0
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; nextln: v3 = bor v4, v5
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return v3
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}
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