71fc16bbeb
* Narrow `allow(dead_code)` declarations Having module wide `allow(dead_code)` may hide some code that's really dead. In this commit I just narrowed the declarations to the specific enum variants that were not used (as it seems reasonable to keep them and their handling in all the matches, for future use). And the compiler found more dead code that I think we can remove safely in the short term. With this, the only files annotated with a module-wide `allow(dead_code)` are isle-generated files. * resurrect some functions as test helpers
1211 lines
38 KiB
Rust
1211 lines
38 KiB
Rust
//! AArch64 ISA definitions: immediate constants.
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// Some variants are never constructed, but we still want them as options in the future.
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#[allow(dead_code)]
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use crate::ir::types::*;
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use crate::ir::Type;
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use crate::isa::aarch64::inst::{OperandSize, ScalarSize};
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use crate::machinst::{AllocationConsumer, PrettyPrint};
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use core::convert::TryFrom;
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use std::string::String;
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/// An immediate that represents the NZCV flags.
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#[derive(Clone, Copy, Debug)]
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pub struct NZCV {
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/// The negative condition flag.
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n: bool,
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/// The zero condition flag.
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z: bool,
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/// The carry condition flag.
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c: bool,
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/// The overflow condition flag.
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v: bool,
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}
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impl NZCV {
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pub fn new(n: bool, z: bool, c: bool, v: bool) -> NZCV {
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NZCV { n, z, c, v }
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}
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/// Bits for encoding.
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pub fn bits(&self) -> u32 {
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(u32::from(self.n) << 3)
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| (u32::from(self.z) << 2)
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| (u32::from(self.c) << 1)
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| u32::from(self.v)
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}
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}
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/// An unsigned 5-bit immediate.
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#[derive(Clone, Copy, Debug)]
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pub struct UImm5 {
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/// The value.
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value: u8,
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}
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impl UImm5 {
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pub fn maybe_from_u8(value: u8) -> Option<UImm5> {
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if value < 32 {
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Some(UImm5 { value })
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} else {
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None
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}
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}
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/// Bits for encoding.
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pub fn bits(&self) -> u32 {
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u32::from(self.value)
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}
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}
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/// A signed, scaled 7-bit offset.
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#[derive(Clone, Copy, Debug)]
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pub struct SImm7Scaled {
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/// The value.
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pub value: i16,
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/// multiplied by the size of this type
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pub scale_ty: Type,
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}
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impl SImm7Scaled {
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/// Create a SImm7Scaled from a raw offset and the known scale type, if
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/// possible.
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pub fn maybe_from_i64(value: i64, scale_ty: Type) -> Option<SImm7Scaled> {
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assert!(scale_ty == I64 || scale_ty == I32 || scale_ty == F64 || scale_ty == I8X16);
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let scale = scale_ty.bytes();
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assert!(scale.is_power_of_two());
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let scale = i64::from(scale);
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let upper_limit = 63 * scale;
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let lower_limit = -(64 * scale);
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if value >= lower_limit && value <= upper_limit && (value & (scale - 1)) == 0 {
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Some(SImm7Scaled {
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value: i16::try_from(value).unwrap(),
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scale_ty,
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})
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} else {
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None
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}
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}
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/// Bits for encoding.
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pub fn bits(&self) -> u32 {
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let ty_bytes: i16 = self.scale_ty.bytes() as i16;
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let scaled: i16 = self.value / ty_bytes;
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assert!(scaled <= 63 && scaled >= -64);
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let scaled: i8 = scaled as i8;
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let encoded: u32 = scaled as u32;
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encoded & 0x7f
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}
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}
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#[derive(Clone, Copy, Debug)]
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pub struct FPULeftShiftImm {
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pub amount: u8,
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pub lane_size_in_bits: u8,
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}
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impl FPULeftShiftImm {
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pub fn maybe_from_u8(amount: u8, lane_size_in_bits: u8) -> Option<Self> {
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debug_assert!(lane_size_in_bits == 32 || lane_size_in_bits == 64);
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if amount < lane_size_in_bits {
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Some(Self {
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amount,
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lane_size_in_bits,
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})
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} else {
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None
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}
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}
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pub fn enc(&self) -> u32 {
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debug_assert!(self.lane_size_in_bits.is_power_of_two());
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debug_assert!(self.lane_size_in_bits > self.amount);
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// The encoding of the immediate follows the table below,
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// where xs encode the shift amount.
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//
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// | lane_size_in_bits | encoding |
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// +------------------------------+
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// | 8 | 0001xxx |
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// | 16 | 001xxxx |
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// | 32 | 01xxxxx |
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// | 64 | 1xxxxxx |
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//
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// The highest one bit is represented by `lane_size_in_bits`. Since
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// `lane_size_in_bits` is a power of 2 and `amount` is less
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// than `lane_size_in_bits`, they can be ORed
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// together to produced the encoded value.
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u32::from(self.lane_size_in_bits | self.amount)
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}
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}
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#[derive(Clone, Copy, Debug)]
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pub struct FPURightShiftImm {
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pub amount: u8,
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pub lane_size_in_bits: u8,
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}
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impl FPURightShiftImm {
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pub fn maybe_from_u8(amount: u8, lane_size_in_bits: u8) -> Option<Self> {
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debug_assert!(lane_size_in_bits == 32 || lane_size_in_bits == 64);
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if amount > 0 && amount <= lane_size_in_bits {
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Some(Self {
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amount,
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lane_size_in_bits,
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})
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} else {
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None
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}
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}
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pub fn enc(&self) -> u32 {
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debug_assert_ne!(0, self.amount);
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// The encoding of the immediate follows the table below,
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// where xs encodes the negated shift amount.
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//
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// | lane_size_in_bits | encoding |
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// +------------------------------+
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// | 8 | 0001xxx |
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// | 16 | 001xxxx |
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// | 32 | 01xxxxx |
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// | 64 | 1xxxxxx |
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//
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// The shift amount is negated such that a shift ammount
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// of 1 (in 64-bit) is encoded as 0b111111 and a shift
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// amount of 64 is encoded as 0b000000,
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// in the bottom 6 bits.
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u32::from((self.lane_size_in_bits * 2) - self.amount)
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}
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}
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/// a 9-bit signed offset.
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#[derive(Clone, Copy, Debug)]
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pub struct SImm9 {
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/// The value.
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pub value: i16,
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}
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impl SImm9 {
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/// Create a signed 9-bit offset from a full-range value, if possible.
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pub fn maybe_from_i64(value: i64) -> Option<SImm9> {
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if value >= -256 && value <= 255 {
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Some(SImm9 {
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value: value as i16,
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})
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} else {
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None
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}
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}
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/// Bits for encoding.
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pub fn bits(&self) -> u32 {
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(self.value as u32) & 0x1ff
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}
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/// Signed value of immediate.
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pub fn value(&self) -> i32 {
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self.value as i32
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}
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}
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/// An unsigned, scaled 12-bit offset.
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#[derive(Clone, Copy, Debug)]
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pub struct UImm12Scaled {
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/// The value.
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pub value: u16,
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/// multiplied by the size of this type
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pub scale_ty: Type,
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}
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impl UImm12Scaled {
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/// Create a UImm12Scaled from a raw offset and the known scale type, if
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/// possible.
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pub fn maybe_from_i64(value: i64, scale_ty: Type) -> Option<UImm12Scaled> {
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// Ensure the type is at least one byte.
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let scale_ty = if scale_ty == B1 { B8 } else { scale_ty };
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let scale = scale_ty.bytes();
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assert!(scale.is_power_of_two());
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let scale = scale as i64;
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let limit = 4095 * scale;
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if value >= 0 && value <= limit && (value & (scale - 1)) == 0 {
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Some(UImm12Scaled {
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value: value as u16,
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scale_ty,
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})
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} else {
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None
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}
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}
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/// Create a zero immediate of this format.
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pub fn zero(scale_ty: Type) -> UImm12Scaled {
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UImm12Scaled { value: 0, scale_ty }
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}
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/// Encoded bits.
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pub fn bits(&self) -> u32 {
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(self.value as u32 / self.scale_ty.bytes()) & 0xfff
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}
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/// Value after scaling.
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pub fn value(&self) -> u32 {
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self.value as u32
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}
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/// The value type which is the scaling base.
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pub fn scale_ty(&self) -> Type {
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self.scale_ty
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}
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}
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/// A shifted immediate value in 'imm12' format: supports 12 bits, shifted
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/// left by 0 or 12 places.
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#[derive(Copy, Clone, Debug)]
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pub struct Imm12 {
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/// The immediate bits.
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pub bits: u16,
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/// Whether the immediate bits are shifted left by 12 or not.
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pub shift12: bool,
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}
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impl Imm12 {
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/// Compute a Imm12 from raw bits, if possible.
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pub fn maybe_from_u64(val: u64) -> Option<Imm12> {
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if val == 0 {
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Some(Imm12 {
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bits: 0,
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shift12: false,
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})
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} else if val < 0xfff {
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Some(Imm12 {
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bits: val as u16,
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shift12: false,
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})
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} else if val < 0xfff_000 && (val & 0xfff == 0) {
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Some(Imm12 {
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bits: (val >> 12) as u16,
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shift12: true,
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})
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} else {
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None
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}
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}
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/// Create a zero immediate of this format.
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pub fn zero() -> Self {
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Imm12 {
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bits: 0,
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shift12: false,
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}
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}
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/// Bits for 2-bit "shift" field in e.g. AddI.
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pub fn shift_bits(&self) -> u32 {
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if self.shift12 {
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0b01
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} else {
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0b00
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}
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}
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/// Bits for 12-bit "imm" field in e.g. AddI.
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pub fn imm_bits(&self) -> u32 {
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self.bits as u32
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}
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}
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/// An immediate for logical instructions.
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub struct ImmLogic {
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/// The actual value.
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value: u64,
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/// `N` flag.
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pub n: bool,
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/// `S` field: element size and element bits.
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pub r: u8,
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/// `R` field: rotate amount.
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pub s: u8,
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/// Was this constructed for a 32-bit or 64-bit instruction?
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pub size: OperandSize,
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}
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impl ImmLogic {
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/// Compute an ImmLogic from raw bits, if possible.
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pub fn maybe_from_u64(value: u64, ty: Type) -> Option<ImmLogic> {
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// Note: This function is a port of VIXL's Assembler::IsImmLogical.
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if ty != I64 && ty != I32 {
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return None;
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}
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let operand_size = OperandSize::from_ty(ty);
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let original_value = value;
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let value = if ty == I32 {
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// To handle 32-bit logical immediates, the very easiest thing is to repeat
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// the input value twice to make a 64-bit word. The correct encoding of that
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// as a logical immediate will also be the correct encoding of the 32-bit
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// value.
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// Avoid making the assumption that the most-significant 32 bits are zero by
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// shifting the value left and duplicating it.
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let value = value << 32;
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value | value >> 32
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} else {
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value
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};
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// Logical immediates are encoded using parameters n, imm_s and imm_r using
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// the following table:
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//
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// N imms immr size S R
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// 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
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// 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
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// 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
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// 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
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// 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
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// 0 11110s xxxxxr 2 UInt(s) UInt(r)
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// (s bits must not be all set)
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//
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// A pattern is constructed of size bits, where the least significant S+1 bits
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// are set. The pattern is rotated right by R, and repeated across a 32 or
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// 64-bit value, depending on destination register width.
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//
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// Put another way: the basic format of a logical immediate is a single
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// contiguous stretch of 1 bits, repeated across the whole word at intervals
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// given by a power of 2. To identify them quickly, we first locate the
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// lowest stretch of 1 bits, then the next 1 bit above that; that combination
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// is different for every logical immediate, so it gives us all the
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// information we need to identify the only logical immediate that our input
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// could be, and then we simply check if that's the value we actually have.
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//
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// (The rotation parameter does give the possibility of the stretch of 1 bits
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// going 'round the end' of the word. To deal with that, we observe that in
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// any situation where that happens the bitwise NOT of the value is also a
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// valid logical immediate. So we simply invert the input whenever its low bit
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// is set, and then we know that the rotated case can't arise.)
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let (value, inverted) = if value & 1 == 1 {
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(!value, true)
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} else {
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(value, false)
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};
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if value == 0 {
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return None;
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}
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// The basic analysis idea: imagine our input word looks like this.
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//
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// 0011111000111110001111100011111000111110001111100011111000111110
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// c b a
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// |<--d-->|
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//
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// We find the lowest set bit (as an actual power-of-2 value, not its index)
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// and call it a. Then we add a to our original number, which wipes out the
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// bottommost stretch of set bits and replaces it with a 1 carried into the
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// next zero bit. Then we look for the new lowest set bit, which is in
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// position b, and subtract it, so now our number is just like the original
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// but with the lowest stretch of set bits completely gone. Now we find the
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// lowest set bit again, which is position c in the diagram above. Then we'll
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// measure the distance d between bit positions a and c (using CLZ), and that
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// tells us that the only valid logical immediate that could possibly be equal
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// to this number is the one in which a stretch of bits running from a to just
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// below b is replicated every d bits.
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fn lowest_set_bit(value: u64) -> u64 {
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let bit = value.trailing_zeros();
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1u64.checked_shl(bit).unwrap_or(0)
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}
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let a = lowest_set_bit(value);
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assert_ne!(0, a);
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let value_plus_a = value.wrapping_add(a);
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let b = lowest_set_bit(value_plus_a);
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let value_plus_a_minus_b = value_plus_a - b;
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let c = lowest_set_bit(value_plus_a_minus_b);
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let (d, clz_a, out_n, mask) = if c != 0 {
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// The general case, in which there is more than one stretch of set bits.
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// Compute the repeat distance d, and set up a bitmask covering the basic
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// unit of repetition (i.e. a word with the bottom d bits set). Also, in all
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// of these cases the N bit of the output will be zero.
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let clz_a = a.leading_zeros();
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let clz_c = c.leading_zeros();
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let d = clz_a - clz_c;
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let mask = (1 << d) - 1;
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(d, clz_a, 0, mask)
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} else {
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(64, a.leading_zeros(), 1, u64::max_value())
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};
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// If the repeat period d is not a power of two, it can't be encoded.
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if !d.is_power_of_two() {
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return None;
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}
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if ((b.wrapping_sub(a)) & !mask) != 0 {
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// If the bit stretch (b - a) does not fit within the mask derived from the
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// repeat period, then fail.
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return None;
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}
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// The only possible option is b - a repeated every d bits. Now we're going to
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// actually construct the valid logical immediate derived from that
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// specification, and see if it equals our original input.
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//
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// To repeat a value every d bits, we multiply it by a number of the form
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// (1 + 2^d + 2^(2d) + ...), i.e. 0x0001000100010001 or similar. These can
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// be derived using a table lookup on CLZ(d).
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const MULTIPLIERS: [u64; 6] = [
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0x0000000000000001,
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0x0000000100000001,
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0x0001000100010001,
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0x0101010101010101,
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0x1111111111111111,
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0x5555555555555555,
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];
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let multiplier = MULTIPLIERS[(u64::from(d).leading_zeros() - 57) as usize];
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let candidate = b.wrapping_sub(a) * multiplier;
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if value != candidate {
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// The candidate pattern doesn't match our input value, so fail.
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return None;
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}
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// We have a match! This is a valid logical immediate, so now we have to
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// construct the bits and pieces of the instruction encoding that generates
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// it.
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// Count the set bits in our basic stretch. The special case of clz(0) == -1
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// makes the answer come out right for stretches that reach the very top of
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// the word (e.g. numbers like 0xffffc00000000000).
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let clz_b = if b == 0 {
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u32::max_value() // -1
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} else {
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b.leading_zeros()
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};
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let s = clz_a.wrapping_sub(clz_b);
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// Decide how many bits to rotate right by, to put the low bit of that basic
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// stretch in position a.
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let (s, r) = if inverted {
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// If we inverted the input right at the start of this function, here's
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// where we compensate: the number of set bits becomes the number of clear
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// bits, and the rotation count is based on position b rather than position
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// a (since b is the location of the 'lowest' 1 bit after inversion).
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// Need wrapping for when clz_b is max_value() (for when b == 0).
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(d - s, clz_b.wrapping_add(1) & (d - 1))
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} else {
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(s, (clz_a + 1) & (d - 1))
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|
};
|
|
|
|
// Now we're done, except for having to encode the S output in such a way that
|
|
// it gives both the number of set bits and the length of the repeated
|
|
// segment. The s field is encoded like this:
|
|
//
|
|
// imms size S
|
|
// ssssss 64 UInt(ssssss)
|
|
// 0sssss 32 UInt(sssss)
|
|
// 10ssss 16 UInt(ssss)
|
|
// 110sss 8 UInt(sss)
|
|
// 1110ss 4 UInt(ss)
|
|
// 11110s 2 UInt(s)
|
|
//
|
|
// So we 'or' (2 * -d) with our computed s to form imms.
|
|
let s = ((d * 2).wrapping_neg() | (s - 1)) & 0x3f;
|
|
debug_assert!(u8::try_from(r).is_ok());
|
|
debug_assert!(u8::try_from(s).is_ok());
|
|
Some(ImmLogic {
|
|
value: original_value,
|
|
n: out_n != 0,
|
|
r: r as u8,
|
|
s: s as u8,
|
|
size: operand_size,
|
|
})
|
|
}
|
|
|
|
/// Returns bits ready for encoding: (N:1, R:6, S:6)
|
|
pub fn enc_bits(&self) -> u32 {
|
|
((self.n as u32) << 12) | ((self.r as u32) << 6) | (self.s as u32)
|
|
}
|
|
|
|
/// Returns the value that this immediate represents.
|
|
pub fn value(&self) -> u64 {
|
|
self.value
|
|
}
|
|
|
|
/// Return an immediate for the bitwise-inverted value.
|
|
pub fn invert(&self) -> ImmLogic {
|
|
// For every ImmLogical immediate, the inverse can also be encoded.
|
|
Self::maybe_from_u64(!self.value, self.size.to_ty()).unwrap()
|
|
}
|
|
}
|
|
|
|
/// An immediate for shift instructions.
|
|
#[derive(Copy, Clone, Debug)]
|
|
pub struct ImmShift {
|
|
/// 6-bit shift amount.
|
|
pub imm: u8,
|
|
}
|
|
|
|
impl ImmShift {
|
|
/// Create an ImmShift from raw bits, if possible.
|
|
pub fn maybe_from_u64(val: u64) -> Option<ImmShift> {
|
|
if val < 64 {
|
|
Some(ImmShift { imm: val as u8 })
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
|
|
/// Get the immediate value.
|
|
pub fn value(&self) -> u8 {
|
|
self.imm
|
|
}
|
|
}
|
|
|
|
/// A 16-bit immediate for a MOVZ instruction, with a {0,16,32,48}-bit shift.
|
|
#[derive(Clone, Copy, Debug)]
|
|
pub struct MoveWideConst {
|
|
/// The value.
|
|
pub bits: u16,
|
|
/// Result is `bits` shifted 16*shift bits to the left.
|
|
pub shift: u8,
|
|
}
|
|
|
|
impl MoveWideConst {
|
|
/// Construct a MoveWideConst from an arbitrary 64-bit constant if possible.
|
|
pub fn maybe_from_u64(value: u64) -> Option<MoveWideConst> {
|
|
let mask0 = 0x0000_0000_0000_ffffu64;
|
|
let mask1 = 0x0000_0000_ffff_0000u64;
|
|
let mask2 = 0x0000_ffff_0000_0000u64;
|
|
let mask3 = 0xffff_0000_0000_0000u64;
|
|
|
|
if value == (value & mask0) {
|
|
return Some(MoveWideConst {
|
|
bits: (value & mask0) as u16,
|
|
shift: 0,
|
|
});
|
|
}
|
|
if value == (value & mask1) {
|
|
return Some(MoveWideConst {
|
|
bits: ((value >> 16) & mask0) as u16,
|
|
shift: 1,
|
|
});
|
|
}
|
|
if value == (value & mask2) {
|
|
return Some(MoveWideConst {
|
|
bits: ((value >> 32) & mask0) as u16,
|
|
shift: 2,
|
|
});
|
|
}
|
|
if value == (value & mask3) {
|
|
return Some(MoveWideConst {
|
|
bits: ((value >> 48) & mask0) as u16,
|
|
shift: 3,
|
|
});
|
|
}
|
|
None
|
|
}
|
|
|
|
pub fn maybe_with_shift(imm: u16, shift: u8) -> Option<MoveWideConst> {
|
|
let shift_enc = shift / 16;
|
|
if shift_enc > 3 {
|
|
None
|
|
} else {
|
|
Some(MoveWideConst {
|
|
bits: imm,
|
|
shift: shift_enc,
|
|
})
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Advanced SIMD modified immediate as used by MOVI/MVNI.
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub struct ASIMDMovModImm {
|
|
imm: u8,
|
|
shift: u8,
|
|
is_64bit: bool,
|
|
shift_ones: bool,
|
|
}
|
|
|
|
impl ASIMDMovModImm {
|
|
/// Construct an ASIMDMovModImm from an arbitrary 64-bit constant, if possible.
|
|
/// Note that the bits in `value` outside of the range specified by `size` are
|
|
/// ignored; for example, in the case of `ScalarSize::Size8` all bits above the
|
|
/// lowest 8 are ignored.
|
|
pub fn maybe_from_u64(value: u64, size: ScalarSize) -> Option<ASIMDMovModImm> {
|
|
match size {
|
|
ScalarSize::Size8 => Some(ASIMDMovModImm {
|
|
imm: value as u8,
|
|
shift: 0,
|
|
is_64bit: false,
|
|
shift_ones: false,
|
|
}),
|
|
ScalarSize::Size16 => {
|
|
let value = value as u16;
|
|
|
|
if value >> 8 == 0 {
|
|
Some(ASIMDMovModImm {
|
|
imm: value as u8,
|
|
shift: 0,
|
|
is_64bit: false,
|
|
shift_ones: false,
|
|
})
|
|
} else if value as u8 == 0 {
|
|
Some(ASIMDMovModImm {
|
|
imm: (value >> 8) as u8,
|
|
shift: 8,
|
|
is_64bit: false,
|
|
shift_ones: false,
|
|
})
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
ScalarSize::Size32 => {
|
|
let value = value as u32;
|
|
|
|
// Value is of the form 0x00MMFFFF.
|
|
if value & 0xFF00FFFF == 0x0000FFFF {
|
|
let imm = (value >> 16) as u8;
|
|
|
|
Some(ASIMDMovModImm {
|
|
imm,
|
|
shift: 16,
|
|
is_64bit: false,
|
|
shift_ones: true,
|
|
})
|
|
// Value is of the form 0x0000MMFF.
|
|
} else if value & 0xFFFF00FF == 0x000000FF {
|
|
let imm = (value >> 8) as u8;
|
|
|
|
Some(ASIMDMovModImm {
|
|
imm,
|
|
shift: 8,
|
|
is_64bit: false,
|
|
shift_ones: true,
|
|
})
|
|
} else {
|
|
// Of the 4 bytes, at most one is non-zero.
|
|
for shift in (0..32).step_by(8) {
|
|
if value & (0xFF << shift) == value {
|
|
return Some(ASIMDMovModImm {
|
|
imm: (value >> shift) as u8,
|
|
shift,
|
|
is_64bit: false,
|
|
shift_ones: false,
|
|
});
|
|
}
|
|
}
|
|
|
|
None
|
|
}
|
|
}
|
|
ScalarSize::Size64 => {
|
|
let mut imm = 0u8;
|
|
|
|
// Check if all bytes are either 0 or 0xFF.
|
|
for i in 0..8 {
|
|
let b = (value >> (i * 8)) as u8;
|
|
|
|
if b == 0 || b == 0xFF {
|
|
imm |= (b & 1) << i;
|
|
} else {
|
|
return None;
|
|
}
|
|
}
|
|
|
|
Some(ASIMDMovModImm {
|
|
imm,
|
|
shift: 0,
|
|
is_64bit: true,
|
|
shift_ones: false,
|
|
})
|
|
}
|
|
_ => None,
|
|
}
|
|
}
|
|
|
|
/// Create a zero immediate of this format.
|
|
pub fn zero(size: ScalarSize) -> Self {
|
|
ASIMDMovModImm {
|
|
imm: 0,
|
|
shift: 0,
|
|
is_64bit: size == ScalarSize::Size64,
|
|
shift_ones: false,
|
|
}
|
|
}
|
|
|
|
/// Returns the value that this immediate represents.
|
|
pub fn value(&self) -> (u8, u32, bool) {
|
|
(self.imm, self.shift as u32, self.shift_ones)
|
|
}
|
|
}
|
|
|
|
/// Advanced SIMD modified immediate as used by the vector variant of FMOV.
|
|
#[derive(Clone, Copy, Debug, PartialEq)]
|
|
pub struct ASIMDFPModImm {
|
|
imm: u8,
|
|
is_64bit: bool,
|
|
}
|
|
|
|
impl ASIMDFPModImm {
|
|
/// Construct an ASIMDFPModImm from an arbitrary 64-bit constant, if possible.
|
|
pub fn maybe_from_u64(value: u64, size: ScalarSize) -> Option<ASIMDFPModImm> {
|
|
// In all cases immediates are encoded as an 8-bit number 0b_abcdefgh;
|
|
// let `D` be the inverse of the digit `d`.
|
|
match size {
|
|
ScalarSize::Size32 => {
|
|
// In this case the representable immediates are 32-bit numbers of the form
|
|
// 0b_aBbb_bbbc_defg_h000 shifted to the left by 16.
|
|
let value = value as u32;
|
|
let b0_5 = (value >> 19) & 0b111111;
|
|
let b6 = (value >> 19) & (1 << 6);
|
|
let b7 = (value >> 24) & (1 << 7);
|
|
let imm = (b0_5 | b6 | b7) as u8;
|
|
|
|
if value == Self::value32(imm) {
|
|
Some(ASIMDFPModImm {
|
|
imm,
|
|
is_64bit: false,
|
|
})
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
ScalarSize::Size64 => {
|
|
// In this case the representable immediates are 64-bit numbers of the form
|
|
// 0b_aBbb_bbbb_bbcd_efgh shifted to the left by 48.
|
|
let b0_5 = (value >> 48) & 0b111111;
|
|
let b6 = (value >> 48) & (1 << 6);
|
|
let b7 = (value >> 56) & (1 << 7);
|
|
let imm = (b0_5 | b6 | b7) as u8;
|
|
|
|
if value == Self::value64(imm) {
|
|
Some(ASIMDFPModImm {
|
|
imm,
|
|
is_64bit: true,
|
|
})
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
_ => None,
|
|
}
|
|
}
|
|
|
|
/// Returns bits ready for encoding.
|
|
pub fn enc_bits(&self) -> u8 {
|
|
self.imm
|
|
}
|
|
|
|
/// Returns the 32-bit value that corresponds to an 8-bit encoding.
|
|
fn value32(imm: u8) -> u32 {
|
|
let imm = imm as u32;
|
|
let b0_5 = imm & 0b111111;
|
|
let b6 = (imm >> 6) & 1;
|
|
let b6_inv = b6 ^ 1;
|
|
let b7 = (imm >> 7) & 1;
|
|
|
|
b0_5 << 19 | (b6 * 0b11111) << 25 | b6_inv << 30 | b7 << 31
|
|
}
|
|
|
|
/// Returns the 64-bit value that corresponds to an 8-bit encoding.
|
|
fn value64(imm: u8) -> u64 {
|
|
let imm = imm as u64;
|
|
let b0_5 = imm & 0b111111;
|
|
let b6 = (imm >> 6) & 1;
|
|
let b6_inv = b6 ^ 1;
|
|
let b7 = (imm >> 7) & 1;
|
|
|
|
b0_5 << 48 | (b6 * 0b11111111) << 54 | b6_inv << 62 | b7 << 63
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for NZCV {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
let fmt = |c: char, v| if v { c.to_ascii_uppercase() } else { c };
|
|
format!(
|
|
"#{}{}{}{}",
|
|
fmt('n', self.n),
|
|
fmt('z', self.z),
|
|
fmt('c', self.c),
|
|
fmt('v', self.v)
|
|
)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for UImm5 {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
format!("#{}", self.value)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for Imm12 {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
let shift = if self.shift12 { 12 } else { 0 };
|
|
let value = u32::from(self.bits) << shift;
|
|
format!("#{}", value)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for SImm7Scaled {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
format!("#{}", self.value)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for FPULeftShiftImm {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
format!("#{}", self.amount)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for FPURightShiftImm {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
format!("#{}", self.amount)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for SImm9 {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
format!("#{}", self.value)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for UImm12Scaled {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
format!("#{}", self.value)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for ImmLogic {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
format!("#{}", self.value())
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for ImmShift {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
format!("#{}", self.imm)
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for MoveWideConst {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
if self.shift == 0 {
|
|
format!("#{}", self.bits)
|
|
} else {
|
|
format!("#{}, LSL #{}", self.bits, self.shift * 16)
|
|
}
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for ASIMDMovModImm {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
if self.is_64bit {
|
|
debug_assert_eq!(self.shift, 0);
|
|
|
|
let enc_imm = self.imm as i8;
|
|
let mut imm = 0u64;
|
|
|
|
for i in 0..8 {
|
|
let b = (enc_imm >> i) & 1;
|
|
|
|
imm |= (-b as u8 as u64) << (i * 8);
|
|
}
|
|
|
|
format!("#{}", imm)
|
|
} else if self.shift == 0 {
|
|
format!("#{}", self.imm)
|
|
} else {
|
|
let shift_type = if self.shift_ones { "MSL" } else { "LSL" };
|
|
format!("#{}, {} #{}", self.imm, shift_type, self.shift)
|
|
}
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for ASIMDFPModImm {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
if self.is_64bit {
|
|
format!("#{}", f64::from_bits(Self::value64(self.imm)))
|
|
} else {
|
|
format!("#{}", f32::from_bits(Self::value32(self.imm)))
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(test)]
|
|
mod test {
|
|
use super::*;
|
|
|
|
#[test]
|
|
fn imm_logical_test() {
|
|
assert_eq!(None, ImmLogic::maybe_from_u64(0, I64));
|
|
assert_eq!(None, ImmLogic::maybe_from_u64(u64::max_value(), I64));
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 1,
|
|
n: true,
|
|
r: 0,
|
|
s: 0,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(1, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 2,
|
|
n: true,
|
|
r: 63,
|
|
s: 0,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(2, I64)
|
|
);
|
|
|
|
assert_eq!(None, ImmLogic::maybe_from_u64(5, I64));
|
|
|
|
assert_eq!(None, ImmLogic::maybe_from_u64(11, I64));
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 248,
|
|
n: true,
|
|
r: 61,
|
|
s: 4,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(248, I64)
|
|
);
|
|
|
|
assert_eq!(None, ImmLogic::maybe_from_u64(249, I64));
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 1920,
|
|
n: true,
|
|
r: 57,
|
|
s: 3,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(1920, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 0x7ffe,
|
|
n: true,
|
|
r: 63,
|
|
s: 13,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(0x7ffe, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 0x30000,
|
|
n: true,
|
|
r: 48,
|
|
s: 1,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(0x30000, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 0x100000,
|
|
n: true,
|
|
r: 44,
|
|
s: 0,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(0x100000, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: u64::max_value() - 1,
|
|
n: true,
|
|
r: 63,
|
|
s: 62,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(u64::max_value() - 1, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 0xaaaaaaaaaaaaaaaa,
|
|
n: false,
|
|
r: 1,
|
|
s: 60,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(0xaaaaaaaaaaaaaaaa, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 0x8181818181818181,
|
|
n: false,
|
|
r: 1,
|
|
s: 49,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(0x8181818181818181, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 0xffc3ffc3ffc3ffc3,
|
|
n: false,
|
|
r: 10,
|
|
s: 43,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(0xffc3ffc3ffc3ffc3, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 0x100000001,
|
|
n: false,
|
|
r: 0,
|
|
s: 0,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(0x100000001, I64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ImmLogic {
|
|
value: 0x1111111111111111,
|
|
n: false,
|
|
r: 0,
|
|
s: 56,
|
|
size: OperandSize::Size64,
|
|
}),
|
|
ImmLogic::maybe_from_u64(0x1111111111111111, I64)
|
|
);
|
|
|
|
for n in 0..2 {
|
|
let types = if n == 0 { vec![I64, I32] } else { vec![I64] };
|
|
for s in 0..64 {
|
|
for r in 0..64 {
|
|
let imm = get_logical_imm(n, s, r);
|
|
for &ty in &types {
|
|
match ImmLogic::maybe_from_u64(imm, ty) {
|
|
Some(ImmLogic { value, .. }) => {
|
|
assert_eq!(imm, value);
|
|
ImmLogic::maybe_from_u64(!value, ty).unwrap();
|
|
}
|
|
None => assert_eq!(0, imm),
|
|
};
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Repeat a value that has `width` bits, across a 64-bit value.
|
|
fn repeat(value: u64, width: u64) -> u64 {
|
|
let mut result = value & ((1 << width) - 1);
|
|
let mut i = width;
|
|
while i < 64 {
|
|
result |= result << i;
|
|
i *= 2;
|
|
}
|
|
result
|
|
}
|
|
|
|
// Get the logical immediate, from the encoding N/R/S bits.
|
|
fn get_logical_imm(n: u32, s: u32, r: u32) -> u64 {
|
|
// An integer is constructed from the n, imm_s and imm_r bits according to
|
|
// the following table:
|
|
//
|
|
// N imms immr size S R
|
|
// 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
|
|
// 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
|
|
// 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
|
|
// 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
|
|
// 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
|
|
// 0 11110s xxxxxr 2 UInt(s) UInt(r)
|
|
// (s bits must not be all set)
|
|
//
|
|
// A pattern is constructed of size bits, where the least significant S+1
|
|
// bits are set. The pattern is rotated right by R, and repeated across a
|
|
// 64-bit value.
|
|
|
|
if n == 1 {
|
|
if s == 0x3f {
|
|
return 0;
|
|
}
|
|
let bits = (1u64 << (s + 1)) - 1;
|
|
bits.rotate_right(r)
|
|
} else {
|
|
if (s >> 1) == 0x1f {
|
|
return 0;
|
|
}
|
|
let mut width = 0x20;
|
|
while width >= 0x2 {
|
|
if (s & width) == 0 {
|
|
let mask = width - 1;
|
|
if (s & mask) == mask {
|
|
return 0;
|
|
}
|
|
let bits = (1u64 << ((s & mask) + 1)) - 1;
|
|
return repeat(bits.rotate_right(r & mask), width.into());
|
|
}
|
|
width >>= 1;
|
|
}
|
|
unreachable!();
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
fn asimd_fp_mod_imm_test() {
|
|
assert_eq!(None, ASIMDFPModImm::maybe_from_u64(0, ScalarSize::Size32));
|
|
assert_eq!(
|
|
None,
|
|
ASIMDFPModImm::maybe_from_u64(0.013671875_f32.to_bits() as u64, ScalarSize::Size32)
|
|
);
|
|
assert_eq!(None, ASIMDFPModImm::maybe_from_u64(0, ScalarSize::Size64));
|
|
assert_eq!(
|
|
None,
|
|
ASIMDFPModImm::maybe_from_u64(10000_f64.to_bits(), ScalarSize::Size64)
|
|
);
|
|
}
|
|
|
|
#[test]
|
|
fn asimd_mov_mod_imm_test() {
|
|
assert_eq!(
|
|
None,
|
|
ASIMDMovModImm::maybe_from_u64(513, ScalarSize::Size16)
|
|
);
|
|
assert_eq!(
|
|
None,
|
|
ASIMDMovModImm::maybe_from_u64(4278190335, ScalarSize::Size32)
|
|
);
|
|
assert_eq!(
|
|
None,
|
|
ASIMDMovModImm::maybe_from_u64(8388608, ScalarSize::Size64)
|
|
);
|
|
|
|
assert_eq!(
|
|
Some(ASIMDMovModImm {
|
|
imm: 66,
|
|
shift: 16,
|
|
is_64bit: false,
|
|
shift_ones: true,
|
|
}),
|
|
ASIMDMovModImm::maybe_from_u64(4390911, ScalarSize::Size32)
|
|
);
|
|
}
|
|
}
|