wasmtime/cranelift/filetests/filetests/isa/aarch64/bitops.clif

test compile
set unwind_info=false
target aarch64

function %a(i8) -> i8 {
block0(v0: i8):
    v1 = bitrev v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: rbit w0, w0
; nextln: lsr w0, w0, #24
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %a(i16) -> i16 {
block0(v0: i16):
    v1 = bitrev v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: rbit w0, w0
; nextln: lsr w0, w0, #16
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %a(i32) -> i32 {
block0(v0: i32):
    v1 = bitrev v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: rbit w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %a(i64) -> i64 {
block0(v0: i64):
    v1 = bitrev v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: rbit x0, x0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret


function %b(i8) -> i8 {
block0(v0: i8):
    v1 = clz v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: uxtb w0, w0
; nextln: clz w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %b(i16) -> i16 {
block0(v0: i16):
    v1 = clz v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: uxth w0, w0
; nextln: clz w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %b(i32) -> i32 {
block0(v0: i32):
    v1 = clz v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: clz w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %b(i64) -> i64 {
block0(v0: i64):
    v1 = clz v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: clz x0, x0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %c(i8) -> i8 {
block0(v0: i8):
    v1 = cls v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: uxtb w0, w0
; nextln: cls w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %c(i16) -> i16 {
block0(v0: i16):
    v1 = cls v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: uxth w0, w0
; nextln: cls w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %c(i32) -> i32 {
block0(v0: i32):
    v1 = cls v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: cls w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %c(i64) -> i64 {
block0(v0: i64):
    v1 = cls v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: cls x0, x0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %d(i8) -> i8 {
block0(v0: i8):
    v1 = ctz v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: rbit w0, w0
; nextln: lsr w0, w0, #24
; nextln: clz w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %d(i16) -> i16 {
block0(v0: i16):
    v1 = ctz v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: rbit w0, w0
; nextln: lsr w0, w0, #16
; nextln: clz w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %d(i32) -> i32 {
block0(v0: i32):
    v1 = ctz v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: rbit w0, w0
; nextln: clz w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %d(i64) -> i64 {
block0(v0: i64):
    v1 = ctz v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: rbit x0, x0
; nextln: clz x0, x0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %d(i64) -> i64 {
block0(v0: i64):
    v1 = popcnt v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: fmov d0, x0
; nextln: cnt v0.8b, v0.8b
; nextln: addv b0, v0.8b
; nextln: umov w0, v0.b[0]
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %d(i32) -> i32 {
block0(v0: i32):
    v1 = popcnt v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: fmov s0, w0
; nextln: cnt v0.8b, v0.8b
; nextln: addv b0, v0.8b
; nextln: umov w0, v0.b[0]
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %d(i16) -> i16 {
block0(v0: i16):
    v1 = popcnt v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: fmov s0, w0
; nextln: cnt v0.8b, v0.8b
; nextln: addp v0.8b, v0.8b, v0.8b
; nextln: umov w0, v0.b[0]
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %d(i8) -> i8 {
block0(v0: i8):
    v1 = popcnt v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: fmov s0, w0
; nextln: cnt v0.8b, v0.8b
; nextln: umov w0, v0.b[0]
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %bextend_b8() -> b32 {
block0:
    v1 = bconst.b8 true
    v2 = bextend.b32 v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: movz x0, #255
; nextln: sxtb w0, w0
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %bextend_b1() -> b32 {
block0:
    v1 = bconst.b1 true
    v2 = bextend.b32 v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: movz x0, #1
; nextln: sbfx w0, w0, #0, #1
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %bnot_i128(i128) -> i128 {
block0(v0: i128):
    v1 = bnot v0
    return v1
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orn x0, xzr, x0
; nextln: orn x1, xzr, x1
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %band_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = band v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: and x0, x0, x2
; nextln: and x1, x1, x3
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %bor_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = bor v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orr x0, x0, x2
; nextln: orr x1, x1, x3
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %bxor_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = bxor v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: eor x0, x0, x2
; nextln: eor x1, x1, x3
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %band_not_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = band_not v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: bic x0, x0, x2
; nextln: bic x1, x1, x3
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %bor_not_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = bor_not v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orn x0, x0, x2
; nextln: orn x1, x1, x3
; nextln: ldp fp, lr, [sp], #16
; nextln: ret

function %bxor_not_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = bxor_not v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: eon x0, x0, x2
; nextln: eon x1, x1, x3
; nextln: ldp fp, lr, [sp], #16
; nextln: ret


function %ishl_i128_i8(i128, i8) -> i128 {
block0(v0: i128, v1: i8):
    v2 = ishl.i128 v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orn w3, wzr, w2
; nextln: lsr x4, x0, #1
; nextln: lsl x1, x1, x2
; nextln: lsr x3, x4, x3
; nextln: lsl x0, x0, x2
; nextln: ands xzr, x2, #64
; nextln: orr x1, x1, x3
; nextln: csel x1, x0, x1, ne
; nextln: csel x0, xzr, x0, ne
; nextln: ldp fp, lr, [sp], #16
; nextln: ret


function %ishl_i128_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = ishl.i128 v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orn w3, wzr, w2
; nextln: lsr x4, x0, #1
; nextln: lsl x1, x1, x2
; nextln: lsr x3, x4, x3
; nextln: lsl x0, x0, x2
; nextln: ands xzr, x2, #64
; nextln: orr x1, x1, x3
; nextln: csel x1, x0, x1, ne
; nextln: csel x0, xzr, x0, ne
; nextln: ldp fp, lr, [sp], #16
; nextln: ret


function %ushr_i128_i8(i128, i8) -> i128 {
block0(v0: i128, v1: i8):
    v2 = ushr.i128 v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orn w3, wzr, w2
; nextln: lsl x4, x1, #1
; nextln: lsr x0, x0, x2
; nextln: lsl x3, x4, x3
; nextln: lsr x1, x1, x2
; nextln: ands xzr, x2, #64
; nextln: orr x0, x0, x3
; nextln: csel x2, xzr, x1, ne
; nextln: csel x0, x1, x0, ne
; nextln: mov x1, x2
; nextln: ldp fp, lr, [sp], #16
; nextln: ret


function %ushr_i128_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = ushr.i128 v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orn w3, wzr, w2
; nextln: lsl x4, x1, #1
; nextln: lsr x0, x0, x2
; nextln: lsl x3, x4, x3
; nextln: lsr x1, x1, x2
; nextln: ands xzr, x2, #64
; nextln: orr x0, x0, x3
; nextln: csel x2, xzr, x1, ne
; nextln: csel x0, x1, x0, ne
; nextln: mov x1, x2
; nextln: ldp fp, lr, [sp], #16
; nextln: ret


function %sshr_i128_i8(i128, i8) -> i128 {
block0(v0: i128, v1: i8):
    v2 = sshr.i128 v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orn w3, wzr, w2
; nextln: lsl x4, x1, #1
; nextln: lsr x0, x0, x2
; nextln: lsl x4, x4, x3
; nextln: asr x3, x1, x2
; nextln: ands xzr, x2, #64
; nextln: asr x1, x1, #63
; nextln: orr x0, x0, x4
; nextln: csel x1, x1, x3, ne
; nextln: csel x0, x3, x0, ne
; nextln: ldp fp, lr, [sp], #16
; nextln: ret


function %sshr_i128_i128(i128, i128) -> i128 {
block0(v0: i128, v1: i128):
    v2 = sshr.i128 v0, v1
    return v2
}

; check: stp fp, lr, [sp, #-16]!
; nextln: mov fp, sp
; nextln: orn w3, wzr, w2
; nextln: lsl x4, x1, #1
; nextln: lsr x0, x0, x2
; nextln: lsl x4, x4, x3
; nextln: asr x3, x1, x2
; nextln: ands xzr, x2, #64
; nextln: asr x1, x1, #63
; nextln: orr x0, x0, x4
; nextln: csel x1, x1, x3, ne
; nextln: csel x0, x3, x0, ne
; nextln: ldp fp, lr, [sp], #16
; nextln: ret