b0b6a8f693
Add a RegBank class for describing CPU register banks. Define register banks for all the ISA stubs. The ARM32 floating point bank in particular requires attention.
19 lines
428 B
Python
19 lines
428 B
Python
"""
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RISC-V register banks.
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"""
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from __future__ import absolute_import
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from cdsl.registers import RegBank
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from .defs import ISA
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# We include `x0`, a.k.a `zero` in the register bank. It will be reserved.
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IntRegs = RegBank(
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'IntRegs', ISA,
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'General purpose registers',
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units=32, prefix='x')
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FloatRegs = RegBank(
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'FloatRegs', ISA,
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'Floating point registers',
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units=32, prefix='f')
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