b077854b57
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
84 lines
1.7 KiB
Plaintext
84 lines
1.7 KiB
Plaintext
test compile precise-output
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target s390x
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function %f1() -> i64, i64, i64, i64 {
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block1:
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v0 = iconst.i64 1
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v1 = iconst.i64 2
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v2 = iconst.i64 3
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v3 = iconst.i64 4
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return v0, v1, v2, v3
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}
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; block0:
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; lghi %r2, 1
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; lghi %r3, 2
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; lghi %r4, 3
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; lghi %r5, 4
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; br %r14
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function %f1() -> i64, i64, i64, i64, i64, i64 {
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block1:
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v0 = iconst.i64 1
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v1 = iconst.i64 2
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v2 = iconst.i64 3
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v3 = iconst.i64 4
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v4 = iconst.i64 5
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v5 = iconst.i64 6
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return v0, v1, v2, v3, v4, v5
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}
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; stmg %r7, %r15, 56(%r15)
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; block0:
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; lghi %r4, 1
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; lgr %r14, %r4
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; lghi %r3, 2
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; lghi %r4, 3
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; lghi %r5, 4
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; lghi %r7, 5
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; lghi %r9, 6
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; stg %r7, 0(%r2)
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; stg %r9, 8(%r2)
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; lgr %r2, %r14
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; lmg %r7, %r15, 56(%r15)
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; br %r14
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function %f3() -> f64, f64, f64, f64 {
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block1:
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v0 = f64const 0x0.0
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v1 = f64const 0x1.0
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v2 = f64const 0x2.0
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v3 = f64const 0x3.0
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return v0, v1, v2, v3
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}
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; block0:
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; bras %r1, 12 ; data.f64 0 ; ld %f0, 0(%r1)
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; bras %r1, 12 ; data.f64 1 ; ld %f2, 0(%r1)
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; bras %r1, 12 ; data.f64 2 ; ld %f4, 0(%r1)
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; bras %r1, 12 ; data.f64 3 ; ld %f6, 0(%r1)
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; br %r14
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function %f4() -> f64, f64, f64, f64, f64, f64 {
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block1:
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v0 = f64const 0x0.0
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v1 = f64const 0x1.0
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v2 = f64const 0x2.0
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v3 = f64const 0x3.0
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v4 = f64const 0x4.0
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v5 = f64const 0x5.0
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return v0, v1, v2, v3, v4, v5
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}
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; block0:
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; bras %r1, 12 ; data.f64 0 ; ld %f0, 0(%r1)
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; bras %r1, 12 ; data.f64 1 ; ld %f2, 0(%r1)
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; bras %r1, 12 ; data.f64 2 ; ld %f4, 0(%r1)
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; bras %r1, 12 ; data.f64 3 ; ld %f6, 0(%r1)
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; bras %r1, 12 ; data.f64 4 ; vleg %v18, 0(%r1), 0
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; bras %r1, 12 ; data.f64 5 ; vleg %v20, 0(%r1), 0
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; vsteg %v18, 0(%r2), 0
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; vsteg %v20, 8(%r2), 0
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; br %r14
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