Trevor Elliott b077854b57 Generate SSA code from returns (#5172) ...

Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.

2022-11-08 16:00:49 -08:00

..

encoding

cranelift: Add Bswap instruction (#1092) (#5147)

2022-10-31 19:30:00 +00:00

inst

Generate SSA code from returns (#5172)

2022-11-08 16:00:49 -08:00

lower

Move bitselect->vselect optimization to x64 back-end (#5191)

2022-11-03 20:17:36 +00:00

abi.rs

Generate SSA code from returns (#5172)

2022-11-08 16:00:49 -08:00

inst.isle

Generate SSA code from returns (#5172)

2022-11-08 16:00:49 -08:00

lower.isle

Support big- and little-endian lane order with bitcast (#5196)

2022-11-07 14:41:10 -08:00

lower.rs

cranelift: Rename i{min,max} to s{min,max} (#5187)

2022-11-03 18:20:33 +00:00

mod.rs

Generate SSA code from returns (#5172)

2022-11-08 16:00:49 -08:00

settings.rs

Change how flags are stored in serialized modules.

2021-04-01 21:39:57 -07:00