Jakob Stoklund Olesen a9e799debb Add an avoid_div_traps setting. ...

This enables code generation that never causes a SIGFPE signal to be
raised from a division instruction. Instead, division and remainder
calculations are protected by explicit traps.

2018-02-16 13:10:29 -08:00

..

arm32

Add register banks for CPU flags to Intel and ARM ISAs.

2017-10-13 14:02:09 -07:00

arm64

Add register banks for CPU flags to Intel and ARM ISAs.

2017-10-13 14:02:09 -07:00

intel

Add an avoid_div_traps setting.

2018-02-16 13:10:29 -08:00

riscv

Add RISC-V encodings for b1 copy/spill/fill.

2018-01-16 09:19:22 -08:00

__init__.py

Fixed for mypy 0.501.

2017-03-03 09:08:28 -08:00