a1b39276e1
The tests for the SIMD floating-point maximum and minimum operations require particular care because the handling of the NaN values is non-deterministic and may vary between platforms. There is no way to match several NaN values in a test, so the solution is to extract the non-deterministic test cases into a separate file that is subsequently replicated for every backend under test, with adjustments made to the expected results. Copyright (c) 2021, Arm Limited.
127 lines
2.0 KiB
Plaintext
127 lines
2.0 KiB
Plaintext
; Test basic code generation for i64 arithmetic WebAssembly instructions.
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test compile
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target aarch64
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target x86_64 haswell
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target x86_64 baseline
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; Constants.
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function %i64_const() -> i64 {
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block0:
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v0 = iconst.i64 0x8765_4321
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return v0
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}
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; Unary operations.
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function %i64_clz(i64) -> i64 {
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block0(v0: i64):
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v1 = clz v0
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return v1
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}
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function %i64_ctz(i64) -> i64 {
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block0(v0: i64):
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v1 = ctz v0
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return v1
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}
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function %i64_popcnt(i64) -> i64 {
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block0(v0: i64):
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v1 = popcnt v0
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return v1
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}
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; Binary operations.
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function %i64_add(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = iadd v0, v1
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return v2
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}
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function %i64_sub(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = isub v0, v1
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return v2
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}
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function %i64_mul(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = imul v0, v1
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return v2
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}
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function %i32_div_s(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sdiv v0, v1
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return v2
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}
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function %i32_div_u(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = udiv v0, v1
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return v2
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}
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function %i32_rem_s(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = srem v0, v1
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return v2
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}
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function %i32_rem_u(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = urem v0, v1
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return v2
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}
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function %i64_and(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = band v0, v1
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return v2
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}
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function %i64_or(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bor v0, v1
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return v2
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}
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function %i64_xor(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bxor v0, v1
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return v2
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}
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function %i64_shl(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = ishl v0, v1
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return v2
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}
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function %i64_shr_s(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = sshr v0, v1
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return v2
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}
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function %i64_shr_u(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = ushr v0, v1
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return v2
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}
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function %i64_rotl(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = rotl v0, v1
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return v2
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}
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function %i64_rotr(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = rotr v0, v1
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return v2
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}
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