02ef6a02b8
* Implement `Extractlane`, `UaddSat`, and `UsubSat` for Cranelift interpreter Implemented the `Extractlane`, `UaddSat`, and `UsubSat` opcodes for the interpreter, and added helper functions for working with SIMD vectors (`extractlanes`, `vectorizelanes`, and `binary_arith`). Copyright (c) 2021, Arm Limited * Re-use tests + constrict Vector assert - Re-use interpreter tests as runtests where supported. - Constrict Vector assertion. - Code style adjustments following feedback. Copyright (c) 2021, Arm Limited * Runtest `i32x4` vectors on AArch64; add `i64x2` tests Copyright (c) 2021, Arm Limited * Add `simd-` prefix to test filenames Copyright (c) 2021, Arm Limited * Return aliased `SmallVec` from `extractlanes` Using a `SmallVec<[i128; 4]>` allows larger-width 128-bit vectors (`i32x4`, `i64x2`, ...) to not cause heap allocations. Copyright (c) 2021, Arm Limited * Accept slice to `vectorizelanes` rather than `Vec` Copyright (c) 2021, Arm Limited
21 lines
714 B
Plaintext
21 lines
714 B
Plaintext
test interpret
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test run
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target aarch64
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; i32x4 vectors aren't supported in `uadd_sat` outside AArch64 at the moment
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function %uaddsat_i32x4(i32x4, i32x4) -> i32x4 {
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block0(v0: i32x4, v1: i32x4):
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v2 = uadd_sat v0, v1
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return v2
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}
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; run: %uaddsat_i32x4([40 40 40 40], [2 2 2 2]) == [42 42 42 42]
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; run: %uaddsat_i32x4([4294967290 2147483640 4294967290 4294967290], [100 100 100 100]) == [4294967295 2147483740 4294967295 4294967295]
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function %uaddsat_i64x2(i64x2, i64x2) -> i64x2 {
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block0(v0: i64x2, v1: i64x2):
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v2 = uadd_sat v0, v1
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return v2
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}
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; run: %uaddsat_i64x2([40 40], [2 2]) == [42 42]
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; run: %uaddsat_i64x2([4294967290 18446744073709551610], [100 100]) == [4294967390 18446744073709551615]
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