62cbb5045e
* riscv64: Swap order of `VecAluRRR` source registers
These were accidentally reversed from what we declare in the isle emit helper
* riscv64: Add SIMD `isub`
* riscv64: Add SIMD `imul`
* riscv64: Add `{u,s}mulhi`
* riscv64: Add `b{and,or,xor}`
* cranelift: Move `imul.i8x16` runtest to separate file
Looks like x86 does not implement it
* riscv64: Better formatting for `VecAluOpRRR`
* cranelift: Enable x86 SIMD tests with `has_sse41=false`
48 lines
2.0 KiB
Plaintext
48 lines
2.0 KiB
Plaintext
test interpret
|
|
test run
|
|
target aarch64
|
|
target s390x
|
|
target x86_64 has_sse41=false
|
|
set enable_simd
|
|
target x86_64
|
|
target x86_64 skylake
|
|
target riscv64 has_v
|
|
|
|
|
|
function %band_i8x16(i8x16, i8x16) -> i8x16 {
|
|
block0(v0:i8x16, v1:i8x16):
|
|
v2 = band v0, v1
|
|
return v2
|
|
}
|
|
; run: %band_i8x16([0xFE 0xDC 0xBA 0x98 0x76 0x54 0x32 0x10 0x01 0x23 0x45 0x67 0x89 0xAB 0xCD 0xEF], [0x01 0x23 0x45 0x67 0x89 0xAB 0xCD 0xEF 0xFE 0xDC 0xBA 0x98 0x76 0x54 0x32 0x10]) == [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
|
|
; run: %band_i8x16([0xFE 0xEE 0xFF 0xFF 0xFE 0xEE 0xFF 0xFF 0xF1 0xFF 0xFE 0xFE 0xF1 0xFF 0xFE 0xFE], [0xDF 0xDB 0xFF 0xFF 0xDF 0xDB 0xFF 0xFF 0xCE 0xFF 0xEF 0xEF 0xCE 0xFF 0xEF 0xEF]) == [0xDE 0xCA 0xFF 0xFF 0xDE 0xCA 0xFF 0xFF 0xC0 0xFF 0xEE 0xEE 0xC0 0xFF 0xEE 0xEE]
|
|
|
|
|
|
function %band_i16x8(i16x8, i16x8) -> i16x8 {
|
|
block0(v0:i16x8, v1:i16x8):
|
|
v2 = band v0, v1
|
|
return v2
|
|
}
|
|
; run: %band_i16x8([0xFEDC 0xBA98 0x7654 0x3210 0x0123 0x4567 0x89AB 0xCDEF], [0x0123 0x4567 0x89AB 0xCDEF 0xFEDC 0xBA98 0x7654 0x3210]) == [0 0 0 0 0 0 0 0]
|
|
; run: %band_i16x8([0xFEEE 0xFFFF 0xFEEE 0xFFFF 0xF1FF 0xFEFE 0xF1FF 0xFEFE], [0xDFDB 0xFFFF 0xDFDB 0xFFFF 0xCEFF 0xEFEF 0xCEFF 0xEFEF]) == [0xDECA 0xFFFF 0xDECA 0xFFFF 0xC0FF 0xEEEE 0xC0FF 0xEEEE]
|
|
|
|
|
|
function %band_i32x4(i32x4, i32x4) -> i32x4 {
|
|
block0(v0:i32x4, v1:i32x4):
|
|
v2 = band v0, v1
|
|
return v2
|
|
}
|
|
; run: %band_i32x4([0xFEDCBA98 0x76543210 0x01234567 0x89ABCDEF], [0x01234567 0x89ABCDEF 0xFEDCBA98 0x76543210]) == [0 0 0 0]
|
|
; run: %band_i32x4([0xFEEEFFFF 0xFEEEFFFF 0xF1FFFEFE 0xF1FFFEFE], [0xDFDBFFFF 0xDFDBFFFF 0xCEFFEFEF 0xCEFFEFEF]) == [0xDECAFFFF 0xDECAFFFF 0xC0FFEEEE 0xC0FFEEEE]
|
|
|
|
|
|
|
|
function %band_i64x2(i64x2, i64x2) -> i64x2 {
|
|
block0(v0:i64x2, v1:i64x2):
|
|
v2 = band v0, v1
|
|
return v2
|
|
}
|
|
; run: %band_i64x2([0xFEDCBA9876543210 0x0123456789ABCDEF], [0x0123456789ABCDEF 0xFEDCBA9876543210]) == [0 0]
|
|
; run: %band_i64x2([0xFEEEFFFFFEEEFFFF 0xF1FFFEFEF1FFFEFE], [0xDFDBFFFFDFDBFFFF 0xCEFFEFEFCEFFEFEF]) == [0xDECAFFFFDECAFFFF 0xC0FFEEEEC0FFEEEE]
|
|
|