602ff71fe4
* riscv64: Use `add.uw` to zero extend * riscv64: Implement `add.uw` optimizations * riscv64: Add `Zba` `iadd+ishl` optimizations * riscv64: Add `shl+uextend` optimizations based on `Zba` * riscv64: Fix some issues with `Zba` instructions * riscv64: Restrict shnadd selection * riscv64: Fix `extend` priorities * riscv64: Remove redundant `addw` rule * riscv64: Specify type for `add` extend rules * riscv64: Use `u64_from_imm64` extractor instead of `uimm8` * riscv64: Restrict `uextend` in `shnadd.uw` rules * riscv64: Use concrete type in `slli.uw` rule * riscv64: Add extra arithmetic extends tests Co-authored-by: Jamey Sharp <jsharp@fastly.com> * riscv64: Make `Adduw` types concrete * riscv64: Add extra arithmetic extend tests * riscv64: Add `sextend`+Arithmetic rules * riscv64: Fix whitespace * cranelift: Move arithmetic extends tests with i128 to separate file --------- Co-authored-by: Jamey Sharp <jsharp@fastly.com>
19 lines
514 B
Plaintext
19 lines
514 B
Plaintext
test interpret
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test run
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set enable_llvm_abi_extensions=true
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target aarch64
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target s390x
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target x86_64
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target riscv64
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target riscv64 has_zba
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function %sext_sshr_i32_i128(i32, i128) -> i64 {
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block0(v0: i32, v1: i128):
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v2 = sshr.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_sshr_i32_i128(0x8000_0000, 0) == 0xFFFFFFFF80000000
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; run: %sext_sshr_i32_i128(0x8000_0000, 32) == 0xFFFFFFFF80000000
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; run: %sext_sshr_i32_i128(0x8000_0000, 0xFFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFF20) == 0xFFFFFFFF80000000
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