638dc4e0b3
This adds full support for all Cranelift SIMD instructions to the s390x target. Everything is matched fully via ISLE. In addition to adding support for many new instructions, and the lower.isle code to match all SIMD IR patterns, this patch also adds ABI support for vector types. In particular, we now need to handle the fact that vector registers 8 .. 15 are partially callee-saved, i.e. the high parts of those registers (which correspond to the old floating-poing registers) are callee-saved, but the low parts are not. This is the exact same situation that we already have on AArch64, and so this patch uses the same solution (the is_included_in_clobbers callback). The bulk of the changes are platform-specific, but there are a few exceptions: - Added ISLE extractors for the Immediate and Constant types, to enable matching the vconst and swizzle instructions. - Added a missing accessor for call_conv to ABISig. - Fixed endian conversion for vector types in data_value.rs to enable their use in runtests on the big-endian platforms. - Enabled (nearly) all SIMD runtests on s390x. [ Two test cases remain disabled due to vector shift count semantics, see below. ] - Enabled all Wasmtime SIMD tests on s390x. There are three minor issues, called out via FIXMEs below, which should be addressed in the future, but should not be blockers to getting this patch merged. I've opened the following issues to track them: - Vector shift count semantics https://github.com/bytecodealliance/wasmtime/issues/4424 - is_included_in_clobbers vs. link register https://github.com/bytecodealliance/wasmtime/issues/4425 - gen_constant callback https://github.com/bytecodealliance/wasmtime/issues/4426 All tests, including all newly enabled SIMD tests, pass on both z14 and z15 architectures.
69 lines
2.3 KiB
Plaintext
69 lines
2.3 KiB
Plaintext
test interpret
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test run
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target aarch64
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target s390x
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function %iaddp_i8x16(i8x16, i8x16) -> i8x16 {
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block0(v0: i8x16, v1: i8x16):
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v2 = iadd_pairwise v0, v1
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return v2
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}
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; run: %iaddp_i8x16([1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16], [17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32]) == [3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63]
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function %iaddp_i16x8(i16x8, i16x8) -> i16x8 {
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block0(v0: i16x8, v1: i16x8):
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v2 = iadd_pairwise v0, v1
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return v2
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}
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; run: %iaddp_i16x8([1 2 3 4 5 6 7 8], [100 99 98 97 96 95 94 93]) == [3 7 11 15 199 195 191 187]
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function %iaddp_i32x4(i32x4, i32x4) -> i32x4 {
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block0(v0: i32x4, v1: i32x4):
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v2 = iadd_pairwise v0, v1
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return v2
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}
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; run: %iaddp_i32x4([1 2 3 4], [5 6 7 8]) == [3 7 11 15]
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; run: %iaddp_i32x4([4294967290 5 4294967290 5], [100 100 100 100]) == [4294967295 4294967295 200 200]
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function %swiden_i8x16(i8x16) -> i16x8 {
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block0(v0: i8x16):
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v1 = swiden_low v0
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v2 = swiden_high v0
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v3 = iadd_pairwise v1, v2
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return v3
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}
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; run: %swiden_i8x16([1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]) == [3 7 11 15 19 23 27 31]
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; run: %swiden_i8x16([-1 2 -3 4 -5 6 -7 8 -9 10 -11 12 -13 14 -15 16]) == [1 1 1 1 1 1 1 1]
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; run: %swiden_i8x16([127 1 126 2 125 3 124 4 123 5 122 6 121 7 120 8]) == [128 128 128 128 128 128 128 128]
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function %uwiden_i8x16(i8x16) -> i16x8 {
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block0(v0: i8x16):
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v1 = uwiden_low v0
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v2 = uwiden_high v0
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v3 = iadd_pairwise v1, v2
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return v3
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}
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; run: %uwiden_i8x16([17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32]) == [35 39 43 47 51 55 59 63]
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; run: %uwiden_i8x16([2 254 3 253 4 252 5 251 6 250 7 249 8 248 9 247]) == [256 256 256 256 256 256 256 256]
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function %swiden_i16x8(i16x8) -> i32x4 {
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block0(v0: i16x8):
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v1 = swiden_low v0
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v2 = swiden_high v0
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v3 = iadd_pairwise v1, v2
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return v3
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}
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; run: %swiden_i16x8([1 2 3 4 5 6 7 8]) == [3 7 11 15]
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; run: %swiden_i16x8([32767 1 32766 3 32765 5 32764 8]) == [32768 32769 32770 32772]
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; run: %swiden_i16x8([-32768 -1 32766 3 32765 5 -32764 -8]) == [-32769 32769 32770 -32772]
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function %uwiden_i16x8(i16x8) -> i32x4 {
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block0(v0: i16x8):
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v1 = uwiden_low v0
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v2 = uwiden_high v0
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v3 = iadd_pairwise v1, v2
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return v3
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}
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; run: %uwiden_i16x8([100 99 98 97 96 95 94 93]) == [199 195 191 187]
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; run: %uwiden_i16x8([65535 1 65534 3 65533 5 65532 8]) == [65536 65537 65538 65540]
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